Apparatus and method for scheduling inference tasks

ABSTRACT

Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

BACKGROUND Field of the Invention

This invention relates generally to the field of graphics processors. More particularly, the invention relates to an apparatus and method for scheduling inference tasks.

Description of the Related Art

Ray tracing is a technique in which a light transport is simulated through physically-based rendering. Widely used in cinematic rendering, it was considered too resource-intensive for real-time performance until just a few years ago. One of the key operations in ray tracing is processing a visibility query for ray-scene intersections known as “ray traversal” which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH).

Rasterization is a technique in which, screen objects are created from 3D models of objects created from a mesh of triangles. The vertices of each triangle intersect with the vertices of other triangles of different shapes and sizes. Each vertex has a position in space as well as information about color, texture and its normal, which is used to determine the way the surface of an object is facing. A rasterization unit converts the triangles of the 3D models into pixels in a 2D screen space and each pixel can be assigned an initial color value based on the vertex data.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

FIG. 1 is a block diagram of a processing system, according to an embodiment.

FIG. 2A is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

FIG. 2B is a block diagram of hardware logic of a graphics processor core block, according to some embodiments described herein.

FIG. 2C illustrates a graphics processing unit (GPU) that includes dedicated sets of graphics processing resources arranged into multi-core groups.

FIG. 2D is a block diagram of general-purpose graphics processing unit (GPGPU) that can be configured as a graphics processor and/or compute accelerator, according to embodiments described herein.

FIG. 3A is a block diagram of a graphics processor, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces.

FIG. 3B illustrates a graphics processor having a tiled architecture, according to embodiments described herein.

FIG. 3C illustrates a compute accelerator, according to embodiments described herein.

FIG. 4 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments.

FIG. 5A illustrates graphics core cluster, according to an embodiment.

FIG. 5B illustrates a vector engine of a graphics core, according to an embodiment.

FIG. 5C illustrates a matrix engine of a graphics core, according to an embodiment.

FIG. 6 illustrates a tile of a multi-tile processor, according to an embodiment.

FIG. 7 is a block diagram illustrating graphics processor instruction formats according to some embodiments.

FIG. 8 is a block diagram of another embodiment of a graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor command format that may be used to program graphics processing pipelines according to some embodiments.

FIG. 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment.

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments.

FIG. 11A is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly 1170, according to some embodiments described herein.

FIG. 11C illustrates a package assembly that includes multiple units of hardware logic chiplets connected to a substrate.

FIG. 11D illustrates a package assembly including interchangeable chiplets, according to an embodiment.

FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.

FIG. 13 illustrates an exemplary graphics processor of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.

FIG. 14 illustrates an additional exemplary graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.

FIG. 15 illustrates an architecture for performing initial training of a machine-learning architecture;

FIG. 16 illustrates how a machine-learning engine is continually trained and updated during runtime;

FIG. 17 illustrates how a machine-learning engine is continually trained and updated during runtime;

FIGS. 18A-B illustrate how machine learning data is shared on a network; and

FIG. 19 illustrates a method for training a machine-learning engine;

FIG. 20 illustrates how nodes exchange ghost region data to perform distributed denoising operations;

FIG. 21 illustrates an architecture in which image rendering and denoising operations are distributed across a plurality of nodes;

FIG. 22 illustrates additional details of an architecture for distributed rendering and denoising;

FIG. 23 illustrates a method for performing distributed rendering and denoising;

FIG. 24 illustrates a machine learning method;

FIG. 25 illustrates a plurality of interconnected general purpose graphics processors;

FIG. 26 illustrates a set of convolutional layers and fully connected layers for a machine learning implementation;

FIG. 27 illustrates an example of a convolutional layer;

FIG. 28 illustrates an example of a set of interconnected nodes in a machine learning implementation;

FIG. 29 illustrates a training framework within which a neural network learns using a training dataset;

FIG. 30A illustrates examples of model parallelism and data parallelism;

FIG. 30B illustrates a system on a chip (SoC);

FIG. 31 illustrates a processing architecture which includes ray tracing cores and tensor cores;

FIG. 32 illustrates an embodiment in which data streaming hardware manages machine learning data within a cache subsystem; and

FIG. 33 illustrates additional details of certain embodiments of the invention;

FIG. 34 illustrates embodiments for performing inference task scheduling; and

FIG. 35 illustrates embodiments for sorting and scheduling for SIMD and SIMT workloads.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

Exemplary Graphics Processor Architectures and Data Types

System Overview

FIG. 1 is a block diagram of a processing system 100, according to an embodiment. Processing system 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, the processing system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices such as within Internet-of-things (IoT) devices with wired or wireless connectivity to a local or wide area network.

In one embodiment, processing system 100 can include, couple with, or be integrated within: a server-based gaming platform; a game console, including a game and media console; a mobile gaming console, a handheld game console, or an online game console. In some embodiments the processing system 100 is part of a mobile phone, smart phone, tablet computing device or mobile Internet-connected device such as a laptop with low internal storage capacity. Processing system 100 can also include, couple with, or be integrated within: a wearable device, such as a smart watch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio or tactile outputs to supplement real world visual, audio or tactile experiences or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) device; or other virtual reality (VR) device. In some embodiments, the processing system 100 includes or is part of a television or set top box device. In one embodiment, processing system 100 can include, couple with, or be integrated within a self-driving vehicle such as a bus, tractor trailer, car, motor or electric power cycle, plane, or glider (or any combination thereof). The self-driving vehicle may use processing system 100 to process the environment sensed around the vehicle.

In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). One or more processor cores 107 may process a different instruction set 109, which may include instructions to facilitate the emulation of other instruction sets. Processor core 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

In some embodiments, the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques. A register file 106 can be additionally included in processor 102 and may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with one or more interface bus(es) 110 to transmit communication signals such as address, data, or control signals between processor 102 and other components in the processing system 100. The interface bus 110, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI express), memory busses, or other types of interface busses. In one embodiment the processor(s) 102 include a memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between a memory device and other components of the processing system 100, while the platform controller hub (PCH) 130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 120 can operate as system memory for the processing system 100, to store data 122 and instructions 121 for use when the one or more processors 102 executes an application or process. The memory controller 116 also couples with an optional external graphics processor 118, which may communicate with the one or more graphics processors 108 in processors 102 to perform graphics and media operations. In some embodiments, graphics, media, and or compute operations may be assisted by an accelerator 112 which is a coprocessor that can be configured to perform a specialized set of graphics, media, or compute operations. For example, in one embodiment the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations. In one embodiment the accelerator 112 is a ray-tracing accelerator that can be used to perform ray-tracing operations in concert with the graphics processor 108. In one embodiment, an external accelerator 119 may be used in place of or in concert with the accelerator 112.

In some embodiments a display device 111 can connect to the processor(s) 102. The display device 111 can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment the display device 111 can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripherals to connect to memory device 120 and processor 102 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, touch sensors 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI express). The touch sensors 125 can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller 134 can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus 110. The audio controller 146, in one embodiment, is a multi-channel high-definition audio controller. In one embodiment the processing system 100 includes an optional legacy I/O controller 140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hub 130 can also connect to one or more Universal Serial Bus (USB) controllers 142 connect input devices, such as keyboard and mouse 143 combinations, a camera 144, or other USB input devices.

It will be appreciated that the processing system 100 shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller 116 and platform controller hub 130 may be integrated into a discreet external graphics processor, such as the external graphics processor 118. In one embodiment the platform controller hub 130 and/or memory controller 116 may be external to the one or more processor(s) 102 and reside in a system chipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In some examples, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in a rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

A data center can utilize a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds can be coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center may, in use, pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and/or artificial intelligence accelerators, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local.

A power supply or source can provide voltage and/or current to processing system 100 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.

FIGS. 2A-2D illustrate computing systems and graphics processors provided by embodiments described herein. The elements of FIGS. 2A-2D having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 can include additional cores up to and including additional core 202N represented by the dashed lined boxes. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments each processor core also has access to one or more shared cached units 206. The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core 210 provides management functionality for the various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multi-threading. In such embodiment, the system agent core 210 includes components for coordinating and operating cores 202A-202N during multi-threaded processing. System agent core 210 may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphics processor 208 to execute graphics processing operations. In some embodiments, the graphics processor 208 couples with the set of shared cache units 206, and the system agent core 210, including the one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208.

In some embodiments, a ring-based interconnect 212 is used to couple the internal components of the processor 200. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, a mesh interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor 208 couples with the ring-based interconnect 212 via an I/O link 213.

The exemplary I/O link 213 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module or a high-bandwidth memory (HBM) module. In some embodiments, each of the processor cores 202A-202N and graphics processor 208 can use the embedded memory module 218 as a shared Last Level Cache.

In some embodiments, processor cores 202A-202N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In one embodiment, processor cores 202A-202N are heterogeneous in terms of computational capability. Additionally, processor 200 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

FIG. 2B is a block diagram of hardware logic of a graphics processor core block 219, according to some embodiments described herein. In some embodiments, elements of FIG. 2B having the same reference numbers (or names) as the elements of any other figure herein may operate or function in a manner similar to that described elsewhere herein. The graphics processor core block 219 is exemplary of one partition of a graphics processor. The graphics processor core block 219 can be included within the integrated graphics processor 208 of FIG. 2A or a discrete graphics processor, parallel processor, and/or compute accelerator. A graphics processor as described herein may include multiple graphics core blocks based on target power and performance envelopes. Each graphics processor core block 219 can include a function block 230 coupled with multiple graphics cores 221A-221F that include modular blocks of fixed function logic and general-purpose programmable logic. The graphics processor core block 219 also includes shared/cache memory 236 that is accessible by all graphics cores 221A-221F, rasterizer logic 237, and additional fixed function logic 238.

In some embodiments, the function block 230 includes a geometry/fixed function pipeline 231 that can be shared by all graphics cores in the graphics processor core block 219. In various embodiments, the geometry/fixed function pipeline 231 includes a 3D geometry pipeline a video front-end unit, a thread spawner and global thread dispatcher, and a unified return buffer manager, which manages unified return buffers. In one embodiment the function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core block 219 and other core blocks within a graphics processor or compute accelerator SoC. The graphics microcontroller 233 is a programmable sub-processor that is configurable to manage various functions of the graphics processor core block 219, including thread dispatch, scheduling, and pre-emption. The media pipeline 234 includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline 234 implement media operations via requests to compute or sampling logic within the graphics cores 221-221F. One or more pixel backends 235 can also be included within the function block 230. The pixel backends 235 include a cache memory to store pixel color values and can perform blend operations and lossless color compression of rendered pixel data.

In one embodiment the graphics SoC interface 232 enables the graphics processor core block 219 to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC or a system host CPU that is coupled with the SoC via a peripheral interface. The graphics SoC interface 232 also enables communication with off-chip memory hierarchy elements such as a shared last level cache memory, system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface 232 can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics processor core block 219 and CPUs within the SoC. The graphics SoC interface 232 can also implement power management controls for the graphics processor core block 219 and enable an interface between a clock domain of the graphics processor core block 219 and other clock domains within the SoC. In one embodiment the graphics SoC interface 232 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline 234 when media operations are to be performed, the geometry and fixed function pipeline 231 when graphics processing operations are to be performed. When compute operations are to be performed, compute dispatch logic can dispatch the commands to the graphics cores 221A-221F, bypassing the geometry and media pipelines.

The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core block 219. In one embodiment the graphics microcontroller 233 can perform graphics and/or compute workload scheduling on the various vector engines 222A-222F, 224A-224F and matrix engines 223A-223F, 225A-225F within the graphics cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics processor core block 219 can submit workloads one of multiple graphics processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment the graphics microcontroller 233 can also facilitate low-power or idle states for the graphics processor core block 219, providing the graphics processor core block 219 with the ability to save and restore registers within the graphics processor core block 219 across low-power state transitions independently from the operating system and/or graphics driver software on the system.

The graphics processor core block 219 may have greater than or fewer than the illustrated graphics cores 221A-221F, up to N modular graphics cores. For each set of N graphics cores, the graphics processor core block 219 can also include shared/cache memory 236, which can be configured as shared memory or cache memory, rasterizer logic 237, and additional fixed function logic 238 to accelerate various graphics and compute processing operations.

Within each graphics cores 221A-221F is set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics cores 221A-221F include multiple vector engines 222A-222F, 224A-224F, matrix acceleration units 223A-223F, 225A-225D, cache/shared local memory (SLM), a sampler 226A-226F, and a ray tracing unit 227A-227F.

The vector engines 222A-222F, 224A-224F are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute/GPGPU programs. The vector engines 222A-222F, 224A-224F can operate at variable vector widths using SIMD, SIMT, or SIMT+SIMD execution modes. The matrix acceleration units 223A-223F, 225A-225D include matrix-matrix and matrix-vector acceleration logic that improves performance on matrix operations, particularly low and mixed precision (e.g., INT8, FP16, BF16) matrix operations used for machine learning. In one embodiment, each of the matrix acceleration units 223A-223F, 225A-225D includes one or more systolic arrays of processing elements that can perform concurrent matrix multiply or dot product operations on matrix elements.

The sampler 226A-226F can read media or texture data into memory and can sample data differently based on a configured sampler state and the texture/media format that is being read. Threads executing on the vector engines 222A-222F, 224A-224F or matrix acceleration units 223A-223F, 225A-225D can make use of the cache/SLM 228A-228F within each execution core. The cache/SLM 228A-228F can be configured as cache memory or as a pool of shared memory that is local to each of the respective graphics cores 221A-221F. The ray tracing units 227A-227F within the graphics cores 221A-221F include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. In one embodiment the ray tracing units 227A-227F include circuitry for performing depth testing and culling (e.g., using a depth buffer or similar arrangement). In one implementation, the ray tracing units 227A-227F perform traversal and intersection operations in concert with image denoising, at least a portion of which may be performed using an associated matrix acceleration unit 223A-223F, 225A-225D.

FIG. 2C illustrates a graphics processing unit (GPU) 239 that includes dedicated sets of graphics processing resources arranged into multi-core groups 240A-240N. The details of multi-core group 240A are illustrated. Multi-core groups 240B-240N may be equipped with the same or similar sets of graphics processing resources.

As illustrated, a multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. A scheduler/dispatcher 241 schedules and dispatches the graphics threads for execution on the various cores 243, 244, 245. In one embodiment the tensor cores 244 are sparse tensor cores with hardware to enable multiplication operations having a zero-value input to be bypassed. The graphics cores 243 of the GPU 239 of FIG. 2C differ in hierarchical abstraction level relative to the graphics cores 221A-221F of FIG. 2B, which are analogous to the multi-core groups 240A-240N of FIG. 2C. The graphics cores 243, tensor cores 244, and ray tracing cores 245 of FIG. 2C are analogous to, respectively, the vector engines 222A-222F, 224A-224F, matrix engines 223A-223F, 225A-225F, and ray tracing units 227A-227F of FIG. 2B.

A set of register files 242 can store operand values used by the cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating-point data elements) and tile registers for storing tensor/matrix values. In one embodiment, the tile registers are implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units 247 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group 240A. One or more texture units 247 can also be used to perform texturing operations, such as texture mapping and sampling. A Level 2 (L2) cache 253 shared by all or a subset of the multi-core groups 240A-240N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across a plurality of multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to a memory 249 which may be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/O devices 252 such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices 252 to the GPU 239 and memory 249. One or more I/O memory management units (IOMMUs) 251 of the I/O circuitry 250 couple the I/O devices 252 directly to the memory 249. In one embodiment, the IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in memory 249. In this embodiment, the I/O devices 252, CPU(s) 246, and GPU 239 may share the same virtual address space.

In one implementation, the IOMMU 251 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within memory 249). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated in FIG. 2C, each of the cores 243, 244, 245 and/or multi-core groups 240A-240N may include translation lookaside buffers (TLBs) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

In one embodiment, the CPUs 246, GPU 239, and I/O devices 252 are integrated on a single semiconductor chip and/or chip package. The memory 249 may be integrated on the same chip or may be coupled to the memory controllers 248 via an off-chip interface. In one implementation, the memory 249 comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles of the embodiments described herein are not limited to this specific implementation.

In one embodiment, the tensor cores 244 include a plurality of functional units specifically designed to perform matrix operations, which are the fundamental compute operation used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores 244 may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores 244. The training of neural networks, in particular, requires a significant number of matrix dot product operations. In order to process an inner-product formulation of an N× N×N matrix multiply, the tensor cores 244 may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.

Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 245 accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 245 include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores 245 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores 245 perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores 244. For example, in one embodiment, the tensor cores 244 implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores 245. However, the CPU(s) 246, graphics cores 243, and/or ray tracing cores 245 may also implement all or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising may be employed in which the GPU 239 is in a computing device coupled to other computing devices over a network or high-speed interconnect. In this embodiment, the interconnected computing devices share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, the ray tracing cores 245 process all BVH traversal and ray-primitive intersections, saving the graphics cores 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 240A can simply launch a ray probe, and the ray tracing cores 245 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute work while the ray tracing cores 245 perform the traversal and intersection operations.

In one embodiment, each ray tracing core 245 includes a traversal unit to perform BVH testing operations and an intersection unit which performs ray-primitive intersection tests. The intersection unit generates a “hit”, “no hit”, or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores 243 and tensor cores 244) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between the graphics cores 243 and ray tracing cores 245.

In one embodiment, the ray tracing cores 245 (and/or other cores 243, 244) include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of unique sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores 245, graphics cores 243 and tensor cores 244 is Vulkan 1.1.85. Note, however, that the underlying principles of the embodiments described herein are not limited to any particular ray tracing ISA.

In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

-   -   Ray Generation—Ray generation instructions may be executed for         each pixel, sample, or other user-defined work assignment.     -   Closest Hit—A closest hit instruction may be executed to locate         the closest intersection point of a ray with primitives within a         scene.     -   Any Hit—An any hit instruction identifies multiple intersections         between a ray and primitives within a scene, potentially to         identify a new closest intersection point.     -   Intersection—An intersection instruction performs a         ray-primitive intersection test and outputs a result.     -   Per-primitive Bounding box Construction—This instruction builds         a bounding box around a given primitive or group of primitives         (e.g., when building a new BVH or other acceleration data         structure).     -   Miss—Indicates that a ray misses all geometry within a scene, or         specified region of a scene.     -   Visit—Indicates the child volumes a ray will traverse.     -   Exceptions—Includes various types of exception handlers (e.g.,         invoked for various error conditions).

In one embodiment the ray tracing cores 245 may be adapted to accelerate general-purpose compute operations that can be accelerated using computational techniques that are analogous to ray intersection tests. A compute framework can be provided that enables shader programs to be compiled into low level instructions and/or primitives that perform general-purpose compute operations via the ray tracing cores. Exemplary computational problems that can benefit from compute operations performed on the ray tracing cores 245 include computations involving beam, wave, ray, or particle propagation within a coordinate space. Interactions associated with that propagation can be computed relative to a geometry or mesh within the coordinate space. For example, computations associated with electromagnetic signal propagation through an environment can be accelerated via the use of instructions or primitives that are executed via the ray tracing cores. Diffraction and reflection of the signals by objects in the environment can be computed as direct ray-tracing analogies.

Ray tracing cores 245 can also be used to perform computations that are not directly analogous to ray tracing. For example, mesh projection, mesh refinement, and volume sampling computations can be accelerated using the ray tracing cores 245. Generic coordinate space calculations, such as nearest neighbor calculations can also be performed. For example, the set of points near a given point can be discovered by defining a bounding box in the coordinate space around the point. BVH and ray probe logic within the ray tracing cores 245 can then be used to determine the set of point intersections within the bounding box. The intersections constitute the origin point and the nearest neighbors to that origin point. Computations that are performed using the ray tracing cores 245 can be performed in parallel with computations performed on the graphics cores 243 and tensor cores 244. A shader compiler can be configured to compile a compute shader or other general-purpose graphics processing program into low level primitives that can be parallelized across the graphics cores 243, tensor cores 244, and ray tracing cores 245.

FIG. 2D is a block diagram of general-purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and/or compute accelerator, according to embodiments described herein. The GPGPU 270 can interconnect with host processors (e.g., one or more CPU(s) 246) and memory 271, 272 via one or more system and/or memory busses. In one embodiment the memory 271 is system memory that may be shared with the one or more CPU(s) 246, while memory 272 is device memory that is dedicated to the GPGPU 270. In one embodiment, components within the GPGPU 270 and memory 272 may be mapped into memory addresses that are accessible to the one or more CPU(s) 246. Access to memory 271 and 272 may be facilitated via a memory controller 268. In one embodiment the memory controller 268 includes an internal direct memory access (DMA) controller 269 or can include logic to perform operations that would otherwise be performed by a DMA controller.

The GPGPU 270 includes multiple cache memories, including an L2 cache 253, L1 cache 254, an instruction cache 255, and shared memory 256, at least a portion of which may also be partitioned as a cache memory. The GPGPU 270 also includes multiple compute units 260A-260N, which represent a hierarchical abstraction level analogous to the graphics cores 221A-221F of FIG. 2B and the multi-core groups 240A-240N of FIG. 2C. Each compute unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic units 263, and scalar logic units 264. The compute units 260A-260N can also include local shared memory 265 and a program counter 266. The compute units 260A-260N can couple with a constant cache 267, which can be used to store constant data, which is data that will not change during the run of kernel or shader program that executes on the GPGPU 270. In one embodiment the constant cache 267 is a scalar data cache and cached data can be fetched directly into the scalar registers 262.

During operation, the one or more CPU(s) 246 can write commands into registers or memory in the GPGPU 270 that has been mapped into an accessible address space. The command processors 257 can read the commands from registers or memory and determine how those commands will be processed within the GPGPU 270. A thread dispatcher 258 can then be used to dispatch threads to the compute units 260A-260N to perform those commands. Each compute unit 260A-260N can execute threads independently of the other compute units. Additionally, each compute unit 260A-260N can be independently configured for conditional computation and can conditionally output the results of computation to memory. The command processors 257 can interrupt the one or more CPU(s) 246 when the submitted commands are complete.

FIGS. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. The elements of FIGS. 3A-3C having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 3A is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a display controller 302 to drive display output data to a display device 318. Display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment the display device 318 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia) VP8, VP9, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media subsystem 315. While 3D pipeline 312 can be used to perform media operations, an embodiment of GPE 310 also includes a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media subsystem 315. The spawned threads perform computations for the media operations on one or more graphics cores included in 3D/Media subsystem 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executing threads spawned by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics cores to process the 3D and media threads. In some embodiments, 3D/Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiled architecture, according to embodiments described herein. In one embodiment the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A within a graphics engine tile 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D may be graphics double data rate (GDDR) memory. The memory devices 326A-326D, in one embodiment, are HBM modules that can be on-die with their respective graphics engine tile 310A-310D. In one embodiment the memory devices 326A-326D are stacked memory devices that can be stacked on top of their respective graphics engine tile 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D reside on separate chiplets, which are bonded to a base die or base substrate, as described on further detail in FIGS. 11B-11D.

The graphics processor 320 may be configured with a non-uniform memory access (NUMA) systemin which memory devices 326A-326D are coupled with associated graphics engine tiles 310A-310D. A given memory device may be accessed by graphics engine tiles other than the tile to which it is directly connected. However, access latency to the memory devices 326A-326D may be lowest when accessing a local tile. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses the tile interconnects 323A-323F to enable communication between cache controllers within the graphics engine tiles 310A-310D to maintain a consistent memory image when more than one cache stores the same memory location.

The graphics processing engine cluster 322 can connect with an on-chip or on-package fabric interconnect 324. In one embodiment the fabric interconnect 324 includes a network processor, network on a chip (NoC), or another switching processor to enable the fabric interconnect 324 to act as a packet switched fabric interconnect that switches data packets between components of the graphics processor 320. The fabric interconnect 324 can enable communication between graphics engine tiles 310A-310D and components such as the video codec engine 306 and one or more copy engines 304. The copy engines 304 can be used to move data out of, into, and between the memory devices 326A-326D and memory that is external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also couple with one or more of the tile interconnects 323A-323F to facilitate or enhance the interconnection between the graphics engine tiles 310A-310D. The fabric interconnect 324 is also configurable to interconnect multiple instances of the graphics processor 320 (e.g., via the host interface 328), enabling tile-to-tile communication between graphics engine tiles 310A-310D of multiple GPUs. In one embodiment, the graphics engine tiles 310A-310D of multiple GPUs can be presented to a host system as a single logical device.

The graphics processor 320 may optionally include a display controller 302 to enable a connection with the display device 318. The graphics processor may also be configured as a graphics or compute accelerator. In the accelerator configuration, the display controller 302 and display device 318 may be omitted.

The graphics processor 320 can connect to a host system via a host interface 328. The host interface 328 can enable communication between the graphics processor 320, system memory, and/or other system components. The host interface 328 can be, for example a PCI express bus or another type of host system interface. For example, the host interface 328 may be an NVLink or NVSwitch interface. The host interface 328 and fabric interconnect 324 can cooperate to enable multiple instances of the graphics processor 320 to act as single logical device. Cooperation between the host interface 328 and fabric interconnect 324 can also enable the individual graphics engine tiles 310A-310D to be presented to the host system as distinct logical graphics devices.

FIG. 3C illustrates a compute accelerator 330, according to embodiments described herein. The compute accelerator 330 can include architectural similarities with the graphics processor 320 of FIG. 3B and is optimized for compute acceleration. A compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic that is optimized for parallel or vector-based general-purpose compute operations. In some embodiments, the compute engine tiles 340A-340D do not include fixed function graphics processing logic, although in one embodiment one or more of the compute engine tiles 340A-340D can include logic to perform media acceleration. The compute engine tiles 340A-340D can connect to memory 326A-326D via memory interconnects 325A-325D. The memory 326A-326D and memory interconnects 325A-325D may be similar technology as in graphics processor 320 or can be different. The graphics compute engine tiles 340A-340D can also be interconnected via a set of tile interconnects 323A-323F and may be connected with and/or interconnected by a fabric interconnect 324. Cross-tile communications can be facilitated via the fabric interconnect 324. The fabric interconnect 324 (e.g., via the host interface 328) can also facilitate communication between compute engine tiles 340A-340D of multiple instances of the compute accelerator 330. In one embodiment the compute accelerator 330 includes a large L3 cache 336 that can be configured as a device-wide cache. The compute accelerator 330 can also connect to a host processor and memory via a host interface 328 in a similar manner as the graphics processor 320 of FIG. 3B.

The compute accelerator 330 can also include an integrated network interface 342. In one embodiment the network interface 342 includes a network processor and controller logic that enables the compute engine cluster 332 to communicate over a physical layer interconnect 344 without requiring data to traverse memory of a host system. In one embodiment, one of the compute engine tiles 340A-340D is replaced by network processor logic and data to be transmitted or received via the physical layer interconnect 344 may be transmitted directly to or from memory 326A-326D. Multiple instances of the compute accelerator 330 may be joined via the physical layer interconnect 344 into a single logical device. Alternatively, the various compute engine tiles 340A-340D may be presented as distinct network accessible compute accelerator devices.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may also represent a graphics engine tile 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are illustrated. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example and in at least one embodiment, a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer 403, which provides a command stream to the 3D pipeline 312 and/or media pipelines 316. Alternatively or additionally, the command streamer 403 may be directly coupled to a unified return buffer 418. The unified return buffer 418 may be communicatively coupled to a graphics core cluster 414. In some embodiments, command streamer 403 is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 403 receives commands from the memory and sends the commands to 3D pipeline 312 and/or media pipeline 316. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline 312 can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline 312 and/or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and media pipeline 316 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core cluster 414. In one embodiment the graphics core cluster 414 include one or more blocks of graphics cores (e.g., graphics core block 415A, graphics core block 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic, such as matrix or AI acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader and/or GPGPU programs, by processing the instructions and dispatching execution threads to the graphics core cluster 414. The graphics core cluster 414 provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic within the graphics core blocks 415A-415B of the graphics core cluster 414 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core cluster 414 includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the graphics cores include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) 107 of FIG. 1 or core 202A-202N as in FIG. 2A.

Output data generated by threads executing on the graphics core cluster 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments the URB 418 may be used to send data between different threads executing on the graphics core cluster 414. In some embodiments the URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.

In some embodiments, graphics core cluster 414 is scalable, such that the cluster includes a variable number of graphics cores, each having a variable number of graphics cores based on the target power and performance level of GPE 410. In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

The graphics core cluster 414 couples with shared function logic 420 that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide specialized supplemental functionality to the graphics core cluster 414. In various embodiments, shared function logic 420 may include, but is not limited to sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more cache(s) 425 within the shared function logic 420. The shared function logic 420 can implement the same or similar functionality as the additional fixed function logic 238 of FIG. 2B.

A shared function is implemented at least in a case where the demand for a given specialized function is insufficient for inclusion within the graphics core cluster 414. Instead, a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic 420 and shared among the execution resources within the graphics core cluster 414. The precise set of functions that are shared between the graphics core cluster 414 and included within the graphics core cluster 414 varies across embodiments. In some embodiments, specific shared functions within the shared function logic 420 that are used extensively by the graphics core cluster 414 may be included within shared function logic 416 within the graphics core cluster 414. In various embodiments, the shared function logic 416 within the graphics core cluster 414 can include some or all logic within the shared function logic 420. In one embodiment, all logic elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core cluster 414. In one embodiment the shared function logic 420 is excluded in favor of the shared function logic 416 within the graphics core cluster 414.

Graphics Processing Resources

FIG. 5A-5C illustrate execution logic including an array of processing elements employed in a graphics processor, according to embodiments described herein. FIG. 5A illustrates graphics core cluster, according to an embodiment. FIG. 5B illustrates a vector engine of a graphics core, according to an embodiment. FIG. 5C illustrates a matrix engine of a graphics core, according to an embodiment. Elements of FIG. 5A-5C having the same reference numbers as the elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited as such. For example, the elements of FIG. 5A-5C can be considered in the context of the graphics processor core block 219 of FIG. 2B, and/or the graphics core blocks 415A-415B of FIG. 4 . In one embodiment, the elements of FIG. 5A-5C have similar functionality to equivalent components of the graphics processor 208 of FIG. 2A, the GPU 239 of FIG. 2C or the GPGPU 270 of FIG. 2D.

As shown in FIG. 5A, in one embodiment the graphics core cluster 414 includes a graphics core block 415, which may be graphics core block 415A or graphics core block 415B of FIG. 4 . The graphics core block 415 can include any number of graphics cores (e.g., graphics core 515A, graphics core 515B, through graphics core 515N). Multiple instances of the graphics core block 415 may be included. In one embodiment the elements of the graphics cores 515A-515N have similar or equivalent functionality as the elements of the graphics cores 221A-221F of FIG. 2B. In such embodiment, the graphics cores 515A-515N each include circuitry including but not limited to vector engines 502A-502N, matrix engines 503A-503N, memory load/store units 504A-504N, instruction caches 505A-505N, data caches/shared local memory 506A-506N, ray tracing units 508A-508N, samplers 510A-2710N. The circuitry of the graphics cores 515A-515N can additionally include fixed function logic 512A-512N. The number of vector engines 502A-502N and matrix engines 503A-503N within the graphics cores 515A-515N of a design can vary based on the workload, performance, and power targets for the design.

With reference to graphics core 515A, the vector engine 502A and matrix engine 503A are configurable to perform parallel compute operations on data in a variety of integer and floating-point data formats based on instructions associated with shader programs. Each vector engine 502A and matrix engine 503A can act as a programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. The vector engine 502A and matrix engine 503A support the processing of variable width vectors at various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. Input data elements can be stored as a packed data type in a register and the vector engine 502A and matrix engine 503A can process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the vector is processed as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. In one embodiment, the vector engine 502A and matrix engine 503A are also configurable for SIMT operation on warps or thread groups of various sizes (e.g., 8, 16, or 32 threads).

Continuing with graphics core 515A, the memory load/store unit 504A services memory access requests that are issued by the vector engine 502A, matrix engine 503A, and/or other components of the graphics core 515A that have access to memory. The memory access request can be processed by the memory load/store unit 504A to load or store the requested data to or from cache or memory into a register file associated with the vector engine 502A and/or matrix engine 503A. The memory load/store unit 504A can also perform prefetching operations. In one embodiment, the memory load/store unit 504A is configured to provide SIMT scatter/gather prefetching or block prefetching for data stored in memory 610, from memory that is local to other tiles via the tile interconnect 608, or from system memory. Prefetching can be performed to a specific L1 cache (e.g., data cache/shared local memory 506A), the L2 cache 604 or the L3 cache 606. In one embodiment, a prefetch to the L3 cache 606 automatically results in the data being stored in the L2 cache 604.

The instruction cache 505A stores instructions to be executed by the graphics core 515A. In one embodiment, the graphics core 515A also includes instruction fetch and prefetch circuitry that fetches or prefetches instructions into the instruction cache 505A. The graphics core 515A also includes instruction decode logic to decode instructions within the instruction cache 505A. The data cache/shared local memory 506A can be configured as a data cache that is managed by a cache controller that implements a cache replacement policy and/or configured as explicitly managed shared memory. The ray tracing unit 508A includes circuitry to accelerate ray tracing operations. The sampler 510A provides texture sampling for 3D operations and media sampling for media operations. The fixed function logic 512A includes fixed function circuitry that is shared between the various instances of the vector engine 502A and matrix engine 503A. Graphics cores 515B-515N can operate in a similar manner as graphics core 515A.

Functionality of the instruction caches 505A-505N, data caches/shared local memory 506A-506N, ray tracing units 508A-508N, samplers 510A-2710N, and fixed function logic 512A-512N corresponds with equivalent functionality in the graphics processor architectures described herein. For example, the instruction caches 505A-505N can operate in a similar manner as instruction cache 255 of FIG. 2D. The data caches/shared local memory 506A-506N, ray tracing units 508A-508N, and samplers 510A-2710N can operate in a similar manner as the cache/SLM 228A-228F, ray tracing units 227A-227F, and samplers 226A-226F of FIG. 2B. The fixed function logic 512A-512N can include elements of the geometry/fixed function pipeline 231 and/or additional fixed function logic 238 of FIG. 2B. In one embodiment, the ray tracing units 508A-508N include circuitry to perform ray tracing acceleration operations performed by the ray tracing cores 245 of FIG. 2C.

As shown in FIG. 5B, in one embodiment the vector engine 502 includes an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and in one embodiment a set of integer SIMD ALUs 535. The GRF 524 and ARF 526 includes the set of general register files and architecture register files associated with each hardware thread that may be active in the vector engine 502. In one embodiment, per thread architectural state is maintained in the ARF 526, while data used during thread execution is stored in the GRF 524. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF 526.

In one embodiment the vector engine 502 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per graphics core, where graphics core resources are divided across logic used to execute multiple simultaneous threads. The number of logical threads that may be executed by the vector engine 502 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In one embodiment, the vector engine 502 can co-issue multiple instructions, which may each be different instructions. The thread arbiter 522 can dispatch the instructions to one of the send unit 530, branch unit 532, or SIMD FPU(s) 534 for execution. Each execution thread can access 128 general-purpose registers within the GRF 524, where each register can store 32 bytes, accessible as a variable width vector of 32-bit data elements. In one embodiment, each thread has access to 4 Kbytes within the GRF 524, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment the vector engine 502 is partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per vector engine 502 can also vary according to embodiments. For example, in one embodiment up to 16 hardware threads are supported. In an embodiment in which seven threads may access 4 Kbytes, the GRF 524 can store a total of 28 Kbytes. Where 16 threads may access 4 Kbytes, the GRF 524 can store a total of 64 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment the vector engine 502 includes one or more SIMD floating point units (FPU(s)) 534 to perform floating-point operations. In one embodiment, the FPU(s) 534 also support integer computation. In one embodiment the FPU(s) 534 can execute up to M number of 32-bit floating-point (or integer) operations, or execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized to perform operations associated with machine learning computations. In one embodiment, the SIMD ALUs are replaced by an additional set of SIMD FPUs 534 that are configurable to perform integer and floating-point operations. In one embodiment, the SIMD FPUs 534 and SIMD ALUs 535 are configurable to execute SIMT programs. In one embodiment, combined SIMD+SIMT operation is supported.

In one embodiment, arrays of multiple instances of the vector engine 502 can be instantiated in a graphics core. For scalability, product architects can choose the exact number of vector engines per graphics core grouping. In one embodiment the vector engine 502 can execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the vector engine 502 is executed on a different channel.

As shown in FIG. 5C, in one embodiment the matrix engine 503 includes an array of processing elements that are configured to perform tensor operations including vector/matrix and matrix/matrix operations, such as but not limited to matrix multiply and/or dot product operations. The matrix engine 503 is configured with M rows and N columns of processing elements (PE 552AA-PE 552MN) that include multiplier and adder circuits organized in a pipelined fashion. In one embodiment, the processing elements 552AA-PE 552MN make up the physical pipeline stages of an N wide and M deep systolic array that can be used to perform vector/matrix or matrix/matrix operations in a data-parallel manner, including matrix multiply, fused multiply-add, dot product or other general matrix-matrix multiplication (GEMM) operations. In one embodiment the matrix engine 503 supports 16-bit floating point operations, as well as 8-bit, 4-bit, 2-bit, and binary integer operations. The matrix engine 503 can also be configured to accelerate specific machine learning operations. In such embodiments, the matrix engine 503 can be configured with support for the bfloat (brain floating point) 16-bit floating point format or a tensor float 32-bit floating point format (TF32) that have different numbers of mantissa and exponent bits relative to Institute of Electrical and Electronics Engineers (IEEE) 754 formats.

In one embodiment, during each cycle, each stage can add the result of operations performed at that stage to the output of the previous stage. In other embodiments, the pattern of data movement between the processing elements 552AA-552MN after a set of computational cycles can vary based on the instruction or macro-operation being performed. For example, in one embodiment partial sum loopback is enabled and the processing elements may instead add the output of a current cycle with output generated in the previous cycle. In one embodiment, the final stage of the systolic array can be configured with a loopback to the initial stage of the systolic array. In such embodiment, the number of physical pipeline stages may be decoupled from the number of logical pipeline stages that are supported by the matrix engine 503. For example, where the processing elements 552AA-552MN are configured as a systolic array of M physical stages, a loopback from stage M to the initial pipeline stage can enable the processing elements 552AA-PE552MN to operate as a systolic array of, for example, 2M, 3M, 4M, etc., logical pipeline stages.

In one embodiment, the matrix engine 503 includes memory 541A-541N, 542A-542M to store input data in the form of row and column data for input matrices. Memory 542A-542M is configurable to store row elements (A0-Am) of a first input matrix and memory 541A-541N is configurable to store column elements (B0-Bn) of a second input matrix. The row and column elements are provided as input to the processing elements 552AA-552MN for processing. In one embodiment, row and column elements of the input matrices can be stored in a systolic register file 540 within the matrix engine 503 before those elements are provided to the memory 541A-541N, 542A-542M. In one embodiment, the systolic register file 540 is excluded and the memory 541A-541N, 542A-542M is loaded from registers in an associated vector engine (e.g., GRF 524 of vector engine 502 of FIG. 5B) or other memory of the graphics core that includes the matrix engine 503 (e.g., data cache/shared local memory 506A for matrix engine 503A of FIG. 5A). Results generated by the processing elements 552AA-552MN are then output to an output buffer and/or written to a register file (e.g., systolic register file 540, GRF 524, data cache/shared local memory 506A-506N) for further processing by other functional units of the graphics processor or for output to memory.

In some embodiments, the matrix engine 503 is configured with support for input sparsity, where multiplication operations for sparse regions of input data can be bypassed by skipping multiply operations that have a zero-value operand. In one embodiment, the processing elements 552AA-552MN are configured to skip the performance of certain operations that have zero value input. In one embodiment, sparsity within input matrices can be detected and operations having known zero output values can be bypassed before being submitted to the processing elements 552AA-552MN. The loading of zero value operands into the processing elements can be bypassed and the processing elements 552AA-552MN can be configured to perform multiplications on the non-zero value input elements. The matrix engine 503 can also be configured with support for output sparsity, such that operations with results that are pre-determined to be zero are bypassed. For input sparsity and/or output sparsity, in one embodiment, metadata is provided to the processing elements 552AA-552MN to indicate, for a processing cycle, which processing elements and/or data channels are to be active during that cycle.

In one embodiment, the matrix engine 503 includes hardware to enable operations on sparse data having a compressed representation of a sparse matrix that stores non-zero values and metadata that identifies the positions of the non-zero values within the matrix. Exemplary compressed representations include but are not limited to compressed tensor representations such as compressed sparse row (CSR), compressed sparse column (CSC), compressed sparse fiber (CSF) representations. Support for compressed representations enable operations to be performed on input in a compressed tensor format without requiring the compressed representation to be decompressed or decoded. In such embodiment, operations can be performed only on non-zero input values and the resulting non-zero output values can be mapped into an output matrix. In some embodiments, hardware support is also provided for machine-specific lossless data compression formats that are used when transmitting data within hardware or across system busses. Such data may be retained in a compressed format for sparse input data and the matrix engine 503 can used the compression metadata for the compressed data to enable operations to be performed on only non-zero values, or to enable blocks of zero data input to be bypassed for multiply operations.

In various embodiments, input data can be provided by a programmer in a compressed tensor representation, or a codec can compress input data into the compressed tensor representation or another sparse data encoding. In addition to support for compressed tensor representations, streaming compression of sparse input data can be performed before the data is provided to the processing elements 552AA-552MN. In one embodiment, compression is performed on data written to a cache memory associated with the graphics core cluster 414, with the compression being performed with an encoding that is supported by the matrix engine 503. In one embodiment, the matrix engine 503 includes support for input having structured sparsity in which a pre-determined level or pattern of sparsity is imposed on input data. This data may be compressed to a known compression ratio, with the compressed data being processed by the processing elements 552AA-552MN according to metadata associated with the compressed data.

FIG. 6 illustrates a tile 600 of a multi-tile processor, according to an embodiment. In one embodiment, the tile 600 is representative of one of the graphics engine tiles 310A-310D of FIG. 3B or compute engine tiles 340A-340D of FIG. 3C. The tile 600 of the multi-tile graphics processor includes an array of graphics core clusters (e.g., graphics core cluster 414A, graphics core cluster 414B, through graphics core cluster 414N), with each graphics core cluster having an array of graphics cores 515A-515N. The tile 600 also includes a global dispatcher 602 to dispatch threads to processing resources of the tile 600.

The tile 600 can include or couple with an L3 cache 606 and memory 610. In various embodiments, the L3 cache 606 may be excluded or the tile 600 can include additional levels of cache, such as an L4 cache. In one embodiment, each instance of the tile 600 in the multi-tile graphics processor has an associated memory 610, such as in FIG. 3B and FIG. 3C. In one embodiment, a multi-tile processor can be configured as a multi-chip module in which the L3 cache 606 and/or memory 610 reside on separate chiplets than the graphics core clusters 414A-414N. In this context, a chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. For example, the L3 cache 606 can be included in a dedicated cache chiplet or can reside on the same chiplet as the graphics core clusters 414A-414N. In one embodiment, the L3 cache 606 can be included in an active base die or active interposer, as illustrated in FIG. 11C.

A memory fabric 603 enables communication among the graphics core clusters 414A-414N, L3 cache 606, and memory 610. An L2 cache 604 couples with the memory fabric 603 and is configurable to cache transactions performed via the memory fabric 603. A tile interconnect 608 enables communication with other tiles on the graphics processors and may be one of tile interconnects 323A-323F of FIGS. 3B and 3C. In embodiments in which the L3 cache 606 is excluded from the tile 600, the L2 cache 604 may be configured as a combined L2/L3 cache. The memory fabric 603 is configurable to route data to the L3 cache 606 or memory controllers associated with the memory 610 based on the presence or absence of the L3 cache 606 in a specific implementation. The L3 cache 606 can be configured as a per-tile cache that is dedicated to processing resources of the tile 600 or may be a partition of a GPU-wide L3 cache.

FIG. 7 is a block diagram illustrating graphics processor instruction formats 700 according to some embodiments. In one or more embodiment, the graphics processor cores support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in a graphics core instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, the graphics processor instruction format 700 described and illustrated are macro-instructions, in that they are instructions supplied to the graphics core, as opposed to micro-operations resulting from instruction decode once the instruction is processed. Thus, a single instruction may cause hardware to perform multiple micro-operations.

In some embodiments, the graphics processor natively supports instructions in a 128-bit instruction format 710. A 64-bit compacted instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field 713. The graphics core hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format 710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that the graphics core is to perform. The graphics cores execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the graphics core performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the graphics core performs each instruction across all data channels of the operands. In some embodiments, instruction control field 714 enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710 an exec-size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field 716 is not available for use in the 64-bit compact instruction format 730.

Some graphics core instructions have up to three operands including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the graphics cores support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726, which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

In one embodiment, the address mode portion of the access/address mode field 726 determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712 bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4, 5, and 6 allow the graphics core to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 742 shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math instruction group 748 performs the arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. The illustrated opcode decode 740, in one embodiment, can be used to determine which portion of a graphics core will be used to execute a decoded instruction. For example, some instructions may be designated as systolic instructions that will be performed by a systolic array. Other instructions, such as ray-tracing instructions (not shown) can be routed to a ray-tracing core or ray-tracing logic within a slice or partition of execution logic.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor 800. Elements of FIG. 8 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex-processing instructions by dispatching execution threads to graphics cores 852A-852B via a thread dispatcher 831.

In some embodiments, graphics cores 852A-852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, graphics cores 852A-852B have an attached L1 cache 851 that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of tessellation output. A tessellator 813 operates at the direction of hull shader 811 and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline 820. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed. The tessellation components can operate based on data received from the vertex shader 807.

In some embodiments, complete geometric objects can be processed by a geometry shader 819 via one or more threads dispatched to graphics cores 852A-852B or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader 819 receives input from the vertex shader 807. In some embodiments, geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, graphics cores 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler 854, caches 851, 858 and graphics cores 852A-852B each have separate memory access paths. In one embodiment the texture cache 858 can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache 878 and depth cache 879 are also available in some embodiments. A pixel operations component 877 performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g., bit block image transfers with blending) are performed by the 2D engine 841, or substituted at display time by the display controller 843 using overlay display planes. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory.

In some embodiments, media pipeline 830 includes a media engine 837 and a video front-end 834. In some embodiments, video front-end 834 receives pipeline commands from the command streamer 803. In some embodiments, media pipeline 830 includes a separate command streamer. In some embodiments, video front-end 834 processes media commands before sending the command to the media engine 837. In some embodiments, media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.

In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples with the graphics processor via the ring interconnect 802, or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 843 couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

In some embodiments, the geometry pipeline 820 and media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor command format 900 that may be used to program graphics processing pipelines according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in FIG. 9A illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format 900 of FIG. 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and a data field 906 for the command. A sub-opcode 905 and a command size 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode 904 and, if present, sub-opcode 905 to determine the operation to perform. The client unit performs the command using information in data field 906. For some commands an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word. Other command formats can be used.

The flow diagram in FIG. 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some embodiments, a pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 913 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures a graphics pipeline for operation and is used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control command 914 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

In some embodiments, commands related to the return buffer state 916 are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination 920, the command sequence is tailored to the 3D pipeline 922 beginning with the 3D pipeline state 930 or the media pipeline 924 beginning at the media pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state 930 commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 932 command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 922 dispatches shader programs to the graphics cores.

In some embodiments, 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back-end operations may also be included for those operations.

In some embodiments, the graphics processor command sequence 910 follows the media pipeline 924 path when performing media operations. In general, the specific use and manner of programming for the media pipeline 924 depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similar manner as the 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched or placed into a command queue before the media object commands 942. In some embodiments, commands for the media pipeline state 940 include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline state 940 also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command 942. Once the pipeline state is configured and media object commands 942 are queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., register write). Output from media pipeline 924 may then be post processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general-purpose processor core(s) 1034. The graphics application 1010 and operating system 1020 each execute in the system memory 1050 of the data processing system.

In some embodiments, 3D graphics application 1010 contains one or more shader programs including shader instructions 1012. The shader language instructions may be in a high-level shader language, such as the High-Level Shader Language (HLSL) of Direct3D, the OpenGL Shader Language (GLSL), and so forth. The application also includes executable instructions 1014 in a machine language suitable for execution by the general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 can support a graphics API 1022 such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-end shader compiler 1027 to convert the shader instructions 1012 into a hardware specific representation. When the OpenGL API is in use, shader instructions 1012 in the GLSL high-level language are passed to a user mode graphics driver 1026 for compilation. In some embodiments, user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, kernel mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 1130 can generate a software simulation 1110 of an IP core design in a high-level programming language (e.g., C/C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design 1115, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3^(rd) party fabrication facility 1165 using non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1150 or wireless connection 1160. The fabrication facility 1165 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly 1170, according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electrically coupled with a bridge 1182 that is configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge 1182 may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

FIG. 11C illustrates a package assembly 1190 that includes multiple units of hardware logic chiplets connected to a substrate 1180. A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be composed from diverse silicon chiplets that are separately manufactured. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally, the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable the interconnection and communication between the different forms of IP within the GPU. IP cores can be manufactured using different process technologies and composed during manufacturing, which avoids the complexity of converging multiple IPs, especially on a large SoC with several flavors IPs, to the same manufacturing process. Enabling the use of multiple process technologies improves the time to market and provides a cost-effective way to create multiple product SKUs. Additionally, the disaggregated IPs are more amenable to being power gated independently, components that are not in use on a given workload can be powered off, reducing overall power consumption.

In various embodiments a package assembly 1190 can include components and chiplets that are interconnected by a fabric 1185 and/or one or more bridges 1187. The chiplets within the package assembly 1190 may have a 2.5D arrangement using Chip-on-Wafer-on-Substrate stacking in which multiple dies are stacked side-by-side on a silicon interposer 1189 that couples the chiplets with the substrate 1180. The substrate 1180 includes electrical connections to the package interconnect 1183. In one embodiment the silicon interposer 1189 is a passive interposer that includes through-silicon vias (TSVs) to electrically couple chiplets within the package assembly 1190 to the substrate 1180. In one embodiment, silicon interposer 1189 is an active interposer that includes embedded logic in addition to TSVs. In such embodiment, the chiplets within the package assembly 1190 are arranged using 3D face to face die stacking on top of the active interposer 1189. The active interposer 1189 can include hardware logic for I/O 1191, cache memory 1192, and other hardware logic 1193, in addition to interconnect fabric 1185 and a silicon bridge 1187. The fabric 1185 enables communication between the various logic chiplets 1172, 1174 and the logic 1191, 1193 within the active interposer 1189. The fabric 1185 may be an NoC interconnect or another form of packet switched fabric that switches data packets between components of the package assembly. For complex assemblies, the fabric 1185 may be a dedicated chiplet enables communication between the various hardware logic of the package assembly 1190.

Bridge structures 1187 within the active interposer 1189 may be used to facilitate a point-to-point interconnect between, for example, logic or I/O chiplets 1174 and memory chiplets 1175. In some implementations, bridge structures 1187 may also be embedded within the substrate 1180. The hardware logic chiplets can include special purpose hardware logic chiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I/O chiplets 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware and can include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory. Cache memory 1192 within the active interposer 1189 (or substrate 1180) can act as a global cache for the package assembly 1190, part of a distributed global cache, or as a dedicated cache for the fabric 1185.

Each chiplet can be fabricated as separate semiconductor die and coupled with a base die that is embedded within or coupled with the substrate 1180. The coupling with the substrate 1180 can be performed via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the various chiplets and logic within the substrate 1180. The interconnect structure 1173 can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic, I/O, and memory chiplets. In one embodiment, an additional interconnect structure couples the active interposer 1189 with the substrate 1180.

In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, a logic or I/O chiplet 1174 and a memory chiplet 1175 can be electrically coupled via a bridge 1187 that is configured to route electrical signals between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1187 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187, in some embodiments, is an Embedded Multi-die Interconnect Bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another chiplet.

FIG. 11D illustrates a package assembly 1194 including interchangeable chiplets 1195, according to an embodiment. The interchangeable chiplets 1195 can be assembled into standardized slots on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to the other bridge interconnects described herein and may be, for example, an EMIB. Memory chiplets can also be connected to logic or I/O chiplets via a bridge interconnect. I/O and logic chiplets can communicate via an interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I/O or memory/cache.

In one embodiment, SRAM and power delivery circuits can be fabricated into one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology relative to the interchangeable chiplets 1195 that are stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, while the interchangeable chiplets can be manufactured using a smaller process technology. One or more of the interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 1194 based on the power, and/or performance targeted for the product that uses the package assembly 1194. Additionally, logic chiplets with a different number of type of functional units can be selected at time of assembly based on the power, and/or performance targeted for the product. Additionally, chiplets containing IP logic cores of differing types can be inserted into the interchangeable chiplet slots, enabling hybrid processor designs that can mix and match different technology IP blocks.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, UART controller 1230, an SPI/SDIO controller 1235, and an I2S/I2C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

FIG. 13 are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 13 illustrates an exemplary graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 14 illustrates an additional exemplary graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor 1310 of FIG. 13 is an example of a low power graphics processor core. Graphics processor 1340 of FIG. 14 is an example of a higher performance graphics processor core. Each of graphics processor 1310 and graphics processor 1340 can be variants of the graphics processor 1210 of FIG. 12 .

As shown in FIG. 13 , graphics processor 1310 includes a vertex processor 1305 and one or more fragment processor(s) 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s) 1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B provide for virtual to physical address mapping for the graphics processor 1310, including for the vertex processor 1305 and/or fragment processor(s) 1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s) 1325A-1325B. In one embodiment the one or more MMU(s) 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s) 1205, image processor 1215, and/or video processor 1220 of FIG. 12 , such that each processor 1205-1220 can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s) 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.

As shown FIG. 14 , graphics processor 1340 includes the one or more MMU(s) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B of the graphics processor 1310 of FIG. 13 . Graphics processor 1340 includes one or more shader core(s) 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The unified shader core architecture is also configurable to execute direct compiled high-level GPGPU programs (e.g., CUDA). The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

Ray Tracing with Machine Learning

As mentioned above, ray tracing is a graphics processing technique in which a light transport is simulated through physically-based rendering. One of the key operations in ray tracing is processing a visibility query which requires traversal and intersection testing of nodes in a bounding volume hierarchy (BVH).

Ray- and path-tracing based techniques compute images by tracing rays and paths through each pixel, and using random sampling to compute advanced effects such as shadows, glossiness, indirect illumination, etc. Using only a few samples is fast but produces noisy images while using many samples produces high quality images, but is cost prohibitive.

Machine learning includes any circuitry, program code, or combination thereof capable of progressively improving performance of a specified task or rendering progressively more accurate predictions or decisions. Some machine learning engines can perform these tasks or render these predictions/decisions without being explicitly programmed to perform the tasks or render the predictions/decisions. A variety of machine learning techniques exist including (but not limited to) supervised and semi-supervised learning, unsupervised learning, and reinforcement learning.

In the last several years, a breakthrough solution to ray-/path-tracing for real-time use has come in the form of “denoising”—the process of using image processing techniques to produce high quality, filtered/denoised images from noisy, low-sample count inputs. The most effective denoising techniques rely on machine learning techniques where a machine-learning engine learns what a noisy image would likely look like if it had been computed with more samples. In one particular implementation, the machine learning is performed by a convolutional neural network (CNN); however, the underlying principles of the invention are not limited to a CNN implementation. In such an implementation, training data is produced with low-sample count inputs and ground-truth. The CNN is trained to predict the converged pixel from a neighborhood of noisy pixel inputs around the pixel in question.

Though not perfect, this AI-based denoising technique has proven surprisingly effective. The caveat, however, is that good training data is required, since the network may otherwise predict the wrong results. For example, if an animated movie studio trained a denoising CNN on past movies with scenes on land and then attempted to use the trained CNN to denoise frames from a new movie set on water, the denoising operation will perform sub-optimally.

To address this problem, learning data can be dynamically gathered, while rendering, and a machine learning engine, such as a CNN, may be continuously trained based on the data on which it is currently being run, thus continuously improving the machine learning engine for the task at hand. Therefore, a training phase may still performed prior to runtime, but continued to adjust the machine learning weights as needed during runtime. Therby, the high cost of computing the reference data required for the training is avoided by restricting the generation of learning data to a sub-region of the image every frame or every N frames. In particular, the noisy inputs of a frame are generated for denoising the full frame with the current network. In addition, a small region of reference pixels are generated and used for continuous training, as described below.

While a CNN implementation is described herein, any form of machine learning engine may be used including, but not limited to systems which perform supervised learning (e.g., building a mathematical model of a set of data that contains both the inputs and the desired outputs), unsupervised learning (e.g., which evaluate the input data for certain types of structure), and/or a combination of supervised and unsupervised learning.

Existing de-noising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined which receives a region of N×N pixels with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive IDs, and albedo and generates a final pixel color. A set of “representative” training data is generated using one frame's worth of low-sample count inputs, and referencing the “desired” pixel colors computed with a very high sample count. The network is trained towards these inputs, generating a set of “ideal” weights for the network. In these implementations, the reference data is used to train the network's weights to most closely match the network's output to the desired result.

At runtime, the given, pre-computed ideal network weights are loaded and the network is initialized. For each frame, a low-sample count image of denoising inputs (i.e., the same as used for training) is generated. For each pixel, the given neighborhood of pixels' inputs is run through the network to predict the “denoised” pixel color, generating a denoised frame.

FIG. 15 illustrates an initial training implementation. A machine learning engine 1500 (e.g., a CNN) receives a region of N×N pixels as high sample count image data 1702 with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive IDs, and albedo and generates final pixel colors. Representative training data is generated using one frame's worth of low-sample count inputs 1501. The network is trained towards these inputs, generating a set of “ideal” weights 1505 which the machine learning engine 1500 subsequently uses to denoise low sample count images at runtime.

To improve the above techniques, the denoising phase to generate new training data every frame or a subset of frames (e.g., every N frames where N=2, 3, 4, 10, 25, etc) is augmented. In particular, as illustrated in FIG. 16 , one or more regions in each frame are chosen, referred to here as “new reference regions” 1602 which are rendered with a high sample count into a separate high sample count buffer 1604. A low sample count buffer 1603 stores the low sample count input frame 1601 (including the low sample region 1604 corresponding to the new reference region 1602).

The location of the new reference region 1602 may be randomly selected. Alternatively, the location of the new reference region 1602 may be adjusted in a pre-specified manner for each new frame (e.g., using a predefined movement of the region between frames, limited to a specified region in the center of the frame, etc).

Regardless of how the new reference region is selected, it is used by the machine learning engine 1600 to continually refine and update the trained weights 1605 used for denoising. In particular, reference pixel colors from each new reference region 1602 and noisy reference pixel inputs from a corresponding low sample count region 1607 are rendered. Supplemental training is then performed on the machine learning engine 1600 using the high-sample-count reference region 1602 and the corresponding low sample count region 1607. In contrast to the initial training, this training is performed continuously during runtime for each new reference region 1602—thereby ensuring that the machine learning engine 1600 is precisely trained. For example, per-pixel data channels (e.g., pixel color, depth, normal, normal deviation, etc) may be evaluated, which the machine learning engine 1600 uses to make adjustments to the trained weights 1605. As in the training case (FIG. 15 ), the machine learning engine 1600 is trained towards a set of ideal weights 1605 for removing noise from the low sample count input frame 1601 to generate the denoised frame 1620. However, the trained weights 1605 are continually updated, based on new image characteristics of new types of low sample count input frames 1601.

The re-training operations performed by the machine learning engine 1600 may be executed concurrently in a background process on the graphics processor unit (GPU) or host processor. The render loop, which may be implemented as a driver component and/or a GPU hardware component, may continuously produce new training data (e.g., in the form of new reference regions 1602) which it places in a queue. The background training process, executed on the GPU or host processor, may continuously read the new training data from this queue, re-trains the machine learning engine 1600, and update it with new weights 1605 at appropriate intervals.

FIG. 17 illustrates an example of one such implementation in which the background training process 1700 is implemented by the host CPU 1710. In particular, the background training process 1700 uses the high sample count new reference region 1602 and the corresponding low sample region 1604 to continually update the trained weights 1605, thereby updating the machine learning engine 1600.

As illustrated in FIG. 18A for the non-limiting example of a multi-player online game, different host machines 1820-1822 individually generate reference regions which a background training process 1700A-C transmits to a server 1800 (e.g., such as a gaming server). The server 1800 then performs training on a machine learning engine 1810 using the new reference regions received from each of the hosts 1821-1822, updating the weights 1805 as previously described. It transmits these weights 1805 to the host machines 1820 which store the weights 1605A-C, thereby updating each individual machine learning engine (not shown). Because the server 1800 may be provided a large number of reference regions in a short period of time, it can efficiently and precisely update the weights for any given application (e.g., an online game) being executed by the users.

As illustrated in FIG. 18B, the different host machines may generate new trained weights (e.g., based on training/reference regions 1602 as previously described) and share the new trained weights with a server 1800 (e.g., such as a gaming server) or, alternatively, use a peer-to-peer sharing protocol. A machine learning management component 1810 on the server generates a set of combined weights 1805 using the new weights received from each of the host machines. The combined weights 1805, for example, may be an average generated from the new weights and continually updated as described herein. Once generated, copies of the combined weights 1605A-C may be transmitted and stored on each of the host machines 1820-1821 which may then use the combined weights as described herein to perform de-noising operations.

The semi-closed loop update mechanism can also be used by the hardware manufacturer. For example, the reference network may be included as part of the driver distributed by the hardware manufacturer. As the driver generates new training data using the techniques described herein and continuously submits these back to the hardware manufacturer, the hardware manufacturer uses this information to continue to improve its machine learning implementations for the next driver update.

In an example implementation (e.g., in batch movie rendering on a render farm), the renderer transmits the newly generated training regions to a dedicated server or database (in that studio's render farm) that aggregates this data from multiple render nodes over time. A separate process on a separate machine continuously improves the studio's dedicated denoising network, and new render jobs always use the latest trained network.

A machine-learning method is illustrated in FIG. 19 . The method may be implemented on the architectures described herein, but is not limited to any particular system or graphics processing architecture.

At 1901, as part of the initial training phase, low sample count image data and high sample count image data are generated for a plurality of image frames. At 1902, a machine-learning denoising engine is trained using the high/low sample count image data. For example, a set of convolutional neural network weights associated with pixel features may be updated in accordance with the training. However, any machine-learning architecture may be used.

At 1903, at runtime, low sample count image frames are generated along with at least one reference region having a high sample count. At 1904, the high sample count reference region is used by the machine-learning engine and/or separate training logic (e.g., background training module 1700) to continually refine the training of the machine learning engine. For example, the high sample count reference region may be used in combination with a corresponding portion of the low sample count image to continue to teach the machine learning engine 1904 how to most effectively perform denoising. In a CNN implementation, for example, this may involve updating the weights associated with the CNN.

Multiple variations described above may be implemented, such as the manner in which the feedback loop to the machine learning engine is configured, the entities which generate the training data, the manner in which the training data is fed back to training engine, and how the improved network is provided to the rendering engines. In addition, while the examples described above perform continuous training using a single reference region, any number of reference regions may be used. Moreover, as previously mentioned, the reference regions may be of different sizes, may be used on different numbers of image frames, and may be positioned in different locations within the image frames using different techniques (e.g., random, according to a predetermined pattern, etc).

In addition, while a convolutional neural network (CNN) is described as one example of a machine-learning engine 1600, the underlying principles of the invention may be implemented using any form of machine learning engine which is capable of continually refining its results using new training data. By way of example, and not limitation, other machine learning implementations include the group method of data handling (GMDH), long short-term memory, deep reservoir computing, deep belief networks, tensor deep stacking networks, and deep predictive coding networks, to name a few.

Apparatus and Method for Efficient Distributed Denoising

As described above, denoising has become a critical feature for real-time ray tracing with smooth, noiseless images. Rendering can be done across a distributed system on multiple devices, but so far the existing denoising frameworks all operate on a single instance on a single machine. If rendering is being done across multiple devices, they may not have all rendered pixels accessible for computing a denoised portion of the image.

A distributed denoising algorithm that works with both artificial intelligence (AI) and non-AI based denoising techniques is presented. Regions of the image are either already distributed across nodes from a distributed render operation, or split up and distributed from a single framebuffer. Ghost regions of neighboring regions needed for computing sufficient denoising are collected from neighboring nodes when needed, and the final resulting tiles are composited into a final image.

Distributed Processing

FIG. 20 illustrates multiple nodes 2021-2023 that perform rendering. While only three nodes are illustrated for simplicity, the underlying principles of the invention are not limited to any particular number of nodes. In fact, a single node may be used to implement certain embodiments of the invention.

Nodes 2021-2023 each render a portion of an image, resulting in regions 2011-2013 in this example. While rectangular regions 2011-2013 are shown in FIG. 20 , regions of any shape may be used and any device can process any number of regions. The regions that are needed by a node to perform a sufficiently smooth denoising operation are referred to as ghost regions 2011-2013. In other words, the ghost regions 2001-2003 represent the entirety of data required to perform denoising at a specified level of quality. Lowering the quality level reduces the size of the ghost region and therefore the amount of data required and raising the quality level increases the ghost region and corresponding data required.

If a node such as node 2021 does have a local copy of a portion of the ghost region 2001 required to denoise its region 2011 at a specified level of quality, the node will retrieve the required data from one or more “adjacent” nodes, such as node 2022 which owns a portion of ghost region 2001 as illustrated. Similarly, if node 2022 does have a local copy of a portion of ghost region 2002 required to denoise its region 2012 at the specified level of quality, node 2022 will retrieve the required ghost region data 2032 from node 2021. The retrieval may be performed over a bus, an interconnect, a high speed memory fabric, a network (e.g., high speed Ethernet), or may even be an on-chip interconnect in a multi-core chip capable of distributing rendering work among a plurality of cores (e.g., used for rendering large images at either extreme resolutions or time varying). Each node 2021-2023 may comprise an individual execution unit or specified set of execution units within a graphics processor.

The specific amount of data to be sent is dependent on the denoising techniques being used. Moreover, the data from the ghost region may include any data needed to improve denoising of each respective region. For example, the ghost region data may include image colors/wavelengths, intensity/alpha data, and/or normals. However, the underlying principles of the invention are not limited to any particular set of ghost region data.

Additional Details

For slower networks or interconnects, compression of this data can be utilized using existing general purpose lossless or lossy compression. Examples include, but are not limited to, zlib, gzip, and Lempel-Ziv-Markov chain algorithm (LZMA). Further content-specific compression may be used by noting that the delta in ray hit information between frames can be quite sparse, and only the samples that contribute to that delta need to be sent when the node already has the collected deltas from previous frames. These can be selectively pushed to nodes that collect those samples, i, or node i can request samples from other nodes. Lossless compression is used for certain types of data and program code while lossy data is used for other types of data.

FIG. 21 illustrates additional details of the interactions between nodes 2021-2022. Each node 2021-2022 includes a ray tracing rendering circuitry 2081-2082 for rendering the respective image regions 2011-2012 and ghost regions 2001-2002. Denoisers 2100-2111 execute denoising operations on the regions 2011-2012, respectively, which each node 2021-2022 is responsible for rendering and denoising. The denoisers 2021-2022, for example, may comprise circuitry, software, or any combination thereof to generate the denoised regions 2121-2122, respectively. As mentioned, when generating denoised regions the denoisers 2021-2022 may need to rely on data within a ghost region owned by a different node (e.g., denoiser 2100 may need data from ghost region 2002 owned by node 2022).

Thus, the denoisers 2100-2111 may generate the denoised regions 2121-2122 using data from regions 2011-2012 and ghost regions 2001-2002, respectively, at least a portion of which may be received from another node. Region data managers 2101-2102 may manage data transfers from ghost regions 2001-2002 as described herein.

Compressor/decompressor units 2131-2132 may perform compression and decompression of the ghost region data exchanged between the nodes 2021-2022, respectively.

For example, region data manager 2101 of node 2021 may, upon request from node 2022, send data from ghost region 2001 to compressor/decompressor 2131, which compresses the data to generate compressed data 2106 which it transmits to node 2022, thereby reducing bandwidth over the interconnect, network, bus, or other data communication link. Compressor/decompressor 2132 of node 2022 then decompresses the compressed data 2106 and denoiser 2111 uses the decompressed ghost data to generate a higher quality denoised region 2012 than would be possible with only data from region 2012. The region data manager 2102 may store the decompressed data from ghost region 2001 in a cache, memory, register file or other storage to make it available to the denoiser 2111 when generating the denoised region 2122. A similar set of operations may be performed to provide the data from ghost region 2002 to denoiser 2100 on node 2021 which uses the data in combination with data from region 2011 to generate a higher quality denoised region 2121.

Grab Data or Render

If the connection between devices such as nodes 2021-2022 is slow (i.e., lower than a threshold latency and/or threshold bandwidth), it may be faster to render ghost regions locally rather than requesting the results from other devices. This can be determined at run-time by tracking network transaction speeds and linearly extrapolated render times for the ghost region size. In such cases where it is faster to render out the entire ghost region, multiple devices may end up rendering the same portions of the image. The resolution of the rendered portion of the ghost regions may be adjusted based on the variance of the base region and the determined degree of blurring.

Load Balancing

Static and/or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2021-2023. For dynamic load balancing, the variance determined by the denoising filter may require both more time in denoising but drive the amount of samples used to render a particular region of the scene, with low variance and blurry regions of the image requiring fewer samples. The specific regions assigned to specific nodes may be adjusted dynamically based on data from previous frames or dynamically communicated across devices as they are rendering so that all devices will have the same amount of work.

FIG. 22 illustrates how a monitor 2201-2202 running on each respective node 2021-2022 collects performance metric data including, but not limited to, the time consumed to transmit data over the network interface 2211-2212, the time consumed when denoising a region (with and without ghost region data), and the time consumed rendering each region/ghost region. The monitors 2201-2202 report these performance metrics back to a manager or load balancer node 2201, which analyzes the data to identify the current workload on each node 2021-2022 and potentially determines a more efficient mode of processing the various denoised regions 2121-2122. The manager node 2201 then distributes new workloads for new regions to the nodes 2021-2022 in accordance with the detected load. For example, the manager node 2201 may transmit more work to those nodes which are not heavily loaded and/or reallocate work from those nodes which are overloaded. In addition, the load balancer node 2201 may transmit a reconfiguration command to adjust the specific manner in which rendering and/or denoising is performed by each of the nodes (some examples of which are described above).

Determining Ghost Regions

The sizes and shapes of the ghost regions 2001-2002 may be determined based on the denoising algorithm implemented by the denoisers 2100-2111. Their respective sizes can then be dynamically modified based on the detected variance of the samples being denoised. The learning algorithm used for AI denoising itself may be used for determining appropriate region sizes, or in other cases such as a bilateral blur the predetermined filter width will determine the size of the ghost regions 2001-2002. In an exemplary implementation which uses a learning algorithm, the machine learning engine may be executed on the manager node 2201 and/or portions of the machine learning may be executed on each of the individual nodes 2021-2023 (see, e.g., FIGS. 18A-B and associated text above).

Gathering the Final Image

The final image may be generated by gathering the rendered and denoised regions from each of the nodes 2021-2023, without the need for the ghost regions or normals. In FIG. 22 , for example, the denoised regions 2121-2122 are transmitted to regions processor 2280 of the manager node 2201 which combines the regions to generate the final denoised image 2290, which is then displayed on a display 2290. The region processor 2280 may combine the regions using a variety of 2D compositing techniques. Although illustrated as separate components, the region processor 2280 and denoised image 2290 may be integral to the display 2290. The various nodes 2021-2022 may use a direct-send technique to transmit the denoised regions 2121-2122 and potentially using various lossy or lossless compression of the region data.

AI denoising is still a costly operation and as gaming moves into the cloud. As such, distributing processing of denoising across multiple nodes 2021-2022 may become required for achieving real-time frame rates for traditional gaming or virtual reality (VR) which requires higher frame rates. Movie studios also often render in large render farms which can be utilized for faster denoising.

An exemplary method for performing distributed rendering and denoising is illustrated in FIG. 23 . The method may be implemented within the context of the system architectures described above, but is not limited to any particular system architecture.

At 2301, graphics work is dispatched to a plurality of nodes which perform ray tracing operations to render a region of an image frame. Each node may already have data required to perform the operations in memory. For example, two or more of the nodes may share a common memory or the local memories of the nodes may already have stored data from prior ray tracing operations. Alternatively, or in addition, certain data may be transmitted to each node.

At 2302, the “ghost region” required for a specified level of denoising (i.e., at an acceptable level of performance) is determined. The ghost region comprises any data required to perform the specified level of denoising, including data owned by one or more other nodes.

At 2303, data related to the ghost regions (or portions thereof) is exchanged between nodes. At 2304 each node performs denoising on its respective region (e.g., using the exchanged data) and at 2305 the results are combined to generate the final denoised image frame.

A manager node or primary node such as shown in FIG. 22 may dispatche the work to the nodes and then combine the work performed by the nodes to generate the final image frame. A peer-based architecture can be used where the nodes are peers which exchange data to render and denoise the final image frame.

The nodes described herein (e.g., nodes 2021-2023) may be graphics processing computing systems interconnected via a high speed network. Alternatively, the nodes may be individual processing elements coupled to a high speed memory fabric. All of the nodes may share a common virtual memory space and/or a common physical memory.

Alternatively, the nodes may be a combination of CPUs and GPUs. For example, the manager node 2201 described above may be a CPU and/or software executed on the CPU and the nodes 2021-2022 may be GPUs and/or software executed on the GPUs. Various different types of nodes may be used while still complying with the underlying principles of the invention.

Example Neural Network Implementations

There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph in which the nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer that are separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. The network nodes are fully connected via edges to the nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of an input layer of a feedforward network are propagated (i.e., “fed forward”) to the nodes of the output layer via an activation function that calculates the states of the nodes of each successive layer in the network based on coefficients (“weights”) respectively associated with each of the edges connecting the layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing a problem being modeled by the network, and adjusting the weights until the network model performs with a minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to the input representing an instance in a training data set is compared to the “correct” labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize that error as the error signal is backward propagated through the layers of the network. The network is considered “trained” when the errors for each of the outputs generated from the instances of the training data set are minimized.

The accuracy of a machine learning algorithm can be affected significantly by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may require a significant amount of time on a conventional general-purpose processor. Accordingly, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed in adjusting the coefficients in neural networks lend themselves naturally to parallel implementations. Specifically, many machine learning algorithms and software applications have been adapted to make use of the parallel processing hardware within general-purpose graphics processing devices.

FIG. 24 is a generalized diagram of a machine learning software stack 2400. A machine learning application 2402 can be configured to train a neural network using a training dataset or to use a trained deep neural network to implement machine intelligence. The machine learning application 2402 can include training and inference functionality for a neural network and/or specialized software that can be used to train a neural network before deployment. The machine learning application 2402 can implement any type of machine intelligence including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 2402 can be enabled via a machine learning framework 2404. The machine learning framework 2404 may be implemented on hardware described herein, such as the processing system 100 comprising the processors and components described herein. The elements described for FIG. 24 having the same or similar names as the elements of any other figure herein describe the same elements as in the other figures, can operate or function in a manner similar to that, can comprise the same components, and can be linked to other entities, as those described elsewhere herein, but are not limited to such. The machine learning framework 2404 can provide a library of machine learning primitives. Machine learning primitives are basic operations that are commonly performed by machine learning algorithms. Without the machine learning framework 2404, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, then re-optimize the computational logic as new parallel processors are developed. Instead, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework 2404. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations that are performed while training a convolutional neural network (CNN). The machine learning framework 2404 can also provide primitives to implement basic linear algebra subprograms performed by many machine-learning algorithms, such as matrix and vector operations.

The machine learning framework 2404 can process input data received from the machine learning application 2402 and generate the appropriate input to a compute framework 2406. The compute framework 2406 can abstract the underlying instructions provided to the GPGPU driver 2408 to enable the machine learning framework 2404 to take advantage of hardware acceleration via the GPGPU hardware 2410 without requiring the machine learning framework 2404 to have intimate knowledge of the architecture of the GPGPU hardware 2410. Additionally, the compute framework 2406 can enable hardware acceleration for the machine learning framework 2404 across a variety of types and generations of the GPGPU hardware 2410.

GPGPU Machine Learning Acceleration

FIG. 25 illustrates a multi-GPU computing system 2500, which may be a variant of the processing system 100. Therefore, the disclosure of any features in combination with the processing system 100 herein also discloses a corresponding combination with multi-GPU computing system 2500, but is not limited to such. The elements of FIG. 25 having the same or similar names as the elements of any other figure herein describe the same elements as in the other figures, can operate or function in a manner similar to that, can comprise the same components, and can be linked to other entities, as those described elsewhere herein, but are not limited to such. The multi-GPU computing system 2500 can include a processor 2502 coupled to multiple GPGPUs 2506A-D via a host interface switch 2504. The host interface switch 2504 may for example be a PCI express switch device that couples the processor 2502 to a PCI express bus over which the processor 2502 can communicate with the set of GPGPUs 2506A-D. Each of the multiple GPGPUs 2506A-D can be an instance of the GPGPU described above. The GPGPUs 2506A-D can interconnect via a set of high-speed point to point GPU to GPU links 2516. The high-speed GPU to GPU links can connect to each of the GPGPUs 2506A-D via a dedicated GPU link. The P2P GPU links 2516 enable direct communication between each of the GPGPUs 2506A-D without requiring communication over the host interface bus to which the processor 2502 is connected. With GPU-to-GPU traffic directed to the P2P GPU links, the host interface bus remains available for system memory access or to communicate with other instances of the multi-GPU computing system 2500, for example, via one or more network devices. Instead of connecting the GPGPUs 2506A-D to the processor 2502 via the host interface switch 2504, the processor 2502 can include direct support for the P2P GPU links 2516 and, thus, connect directly to the GPGPUs 2506A-D.

Machine Learning Neural Network Implementations

The computing architecture described herein can be configured to perform the types of parallel processing that is particularly suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions having a graph relationship. As is well-known in the art, there are a variety of types of neural network implementations used in machine learning. One exemplary type of neural network is the feedforward network, as previously described.

A second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network for processing data having a known, grid-like topology, such as image data. Accordingly, CNNs are commonly used for compute vision and image recognition applications, but they also may be used for other types of pattern recognition such as speech and language processing. The nodes in the CNN input layer are organized into a set of “filters” (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computations for a CNN include applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output may be referred to as the feature map. For example, the input to a convolution layer can be a multidimensional array of data that defines the various color components of an input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process for the neural network.

Recurrent neural networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for a RNN includes cycles. The cycles represent the influence of a present value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent input in a sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed.

The figures described below present exemplary feedforward, CNN, and RNN networks, as well as describe a general process for respectively training and deploying each of those types of networks. It will be understood that these descriptions are exemplary and non-limiting and the concepts illustrated can be applied generally to deep neural networks and machine learning techniques in general.

The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, as opposed to shallow neural networks that include only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multistep pattern recognition that results in reduced output error relative to shallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network which represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without requiring hand crafted feature engineering to be performed for the model. Instead, deep neural networks can learn features based on statistical structure or correlation within the input data. The learned features can be provided to a mathematical model that can map detected features to an output. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different task.

Once the neural network is structured, a learning model can be applied to the network to train the network to perform specific tasks. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function and an error value is calculated for each of the neurons in the output layer. The error values are then propagated backwards until each neuron has an associated error value which roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm, such as the stochastic gradient descent algorithm, to update the weights of the of the neural network.

FIGS. 26-27 illustrate an exemplary convolutional neural network. FIG. 26 illustrates various layers within a CNN. As shown in FIG. 26 , an exemplary CNN used to model image processing can receive input 2602 describing the red, green, and blue (RGB) components of an input image. The input 2602 can be processed by multiple convolutional layers (e.g., convolutional layer 2604, convolutional layer 2606). The output from the multiple convolutional layers may optionally be processed by a set of fully connected layers 2608. Neurons in a fully connected layer have full connections to all activations in the previous layer, as previously described for a feedforward network. The output from the fully connected layers 2608 can be used to generate an output result from the network. The activations within the fully connected layers 2608 can be computed using matrix multiplication instead of convolution. Not all CNN implementations make use of fully connected layers. For example, in some implementations the convolutional layer 2606 can generate output for the CNN.

The convolutional layers are sparsely connected, which differs from traditional neural network configuration found in the fully connected layers 2608. Traditional neural network layers are fully connected, such that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of a field is input (instead of the respective state value of each of the nodes in the field) to the nodes of the subsequent layer, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that enables the CNN to scale to process large images.

FIG. 27 illustrates exemplary computation stages within a convolutional layer of a CNN. Input to a convolutional layer 2712 of a CNN can be processed in three stages of a convolutional layer 2714. The three stages can include a convolution stage 2716, a detector stage 2718, and a pooling stage 2720. The convolution layer 2714 can then output data to a successive convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

In the convolution stage 2716 performs several convolutions in parallel to produce a set of linear activations. The convolution stage 2716 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage computes the output of functions (e.g., neurons) that are connected to specific regions in the input, which can be determined as the local region associated with the neuron. The neurons compute a dot product between the weights of the neurons and the region in the local input to which the neurons are connected. The output from the convolution stage 2716 defines a set of linear activations that are processed by successive stages of the convolutional layer 2714.

The linear activations can be processed by a detector stage 2718. In the detector stage 2718, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the nonlinear properties of the overall network without affecting the receptive fields of the convolution layer. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max (0, x), such that the activation is thresholded at zero.

The pooling stage 2720 uses a pooling function that replaces the output of the convolutional layer 2706 with a summary statistic of the nearby outputs. The pooling function can be used to introduce translation invariance into the neural network, such that small translations to the input do not change the pooled outputs. Invariance to local translation can be useful in scenarios where the presence of a feature in the input data is more important than the precise location of the feature. Various types of pooling functions can be used during the pooling stage 2720, including max pooling, average pooling, and I2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute and additional convolution stage having an increased stride relative to previous convolution stages.

The output from the convolutional layer 2714 can then be processed by the next layer 2722. The next layer 2722 can be an additional convolutional layer or one of the fully connected layers 2708. For example, the first convolutional layer 2704 of FIG. 27 can output to the second convolutional layer 2706, while the second convolutional layer can output to a first layer of the fully connected layers 2808.

FIG. 28 illustrates an exemplary recurrent neural network 2800. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on a prior sequence of inputs. For example, an RNN may be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The illustrated RNN 2800 can be described has having an input layer 2802 that receives an input vector, hidden layers 2804 to implement a recurrent function, a feedback mechanism 2805 to enable a ‘memory’ of previous states, and an output layer 2806 to output a result. The RNN 2800 operates based on time-steps. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism 2805. For a given time step, the state of the hidden layers 2804 is defined by the previous state and the input at the current time step. An initial input (x1) at a first time step can be processed by the hidden layer 2804. A second input (x2) can be processed by the hidden layer 2804 using state information that is determined during the processing of the initial input (x1). A given state can be computed as s_t=f(Ux_t+Ws_(t−1)), where U and W are parameter matrices. The function f is generally a nonlinearity, such as the hyperbolic tangent function (Tan h) or a variant of the rectifier function f(x)=max (0, x). However, the specific mathematical function used in the hidden layers 2804 can vary depending on the specific implementation details of the RNN 2800.

In addition to the basic CNN and RNN networks described, variations on those networks may be enabled. One example RNN variant is the long short term memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that may be necessary for processing longer sequences of language. A variant on the CNN is a convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network that is composed of multiple layers of stochastic (random) variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide pre-train neural networks by determining an optimal initial set of weights for the neural network.

FIG. 29 illustrates training and deployment of a deep neural network. Once a given network has been structured for a task the neural network is trained using a training dataset 2902. Various training frameworks 2904 have been developed to enable hardware acceleration of the training process. For example, the machine learning framework described above may be configured as a training framework. The training framework 2904 can hook into an untrained neural network 2906 and enable the untrained neural net to be trained using the parallel processing resources described herein to generate a trained neural net 2908.

To start the training process the initial weights may be chosen randomly or by pre-training using a deep belief network. The training cycle then be performed in either a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training dataset 2902 includes input paired with the desired output for the input, or where the training dataset includes input having known output and the output of the neural network is manually graded. The network processes the inputs and compares the resulting outputs against a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 2904 can adjust to adjust the weights that control the untrained neural network 2906. The training framework 2904 can provide tools to monitor how well the untrained neural network 2906 is converging towards a model suitable to generating correct answers based on known input data. The training process occurs repeatedly as the weights of the network are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with a trained neural net 2908. The trained neural network 2908 can then be deployed to implement any number of machine learning operations.

Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning the training dataset 2902 will include input data without any associated output data. The untrained neural network 2906 can learn groupings within the unlabeled input and can determine how individual inputs are related to the overall dataset. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 2907 capable of performing operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in an input dataset that deviate from the normal patterns of the data.

Variations on supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which in the training dataset 2902 includes a mix of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 2908 to adapt to the new data 2912 without forgetting the knowledge instilled within the network during initial training.

Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of computational nodes can be used to accelerate the training process.

FIG. 30A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes such as the nodes described above to perform supervised or unsupervised training of a neural network. The distributed computational nodes can each include one or more host processors and one or more of the general-purpose processing nodes, such as a highly-parallel general-purpose graphics processing unit. As illustrated, distributed learning can be performed model parallelism 3002, data parallelism 3004, or a combination of model and data parallelism.

In model parallelism 3002, different computational nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of the neural network enables the training of very large neural networks in which the weights of all layers would not fit into the memory of a single computational node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

In data parallelism 3004, the different nodes of the distributed network have a complete instance of the model and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, data parallel training approaches all require a technique of combining results and synchronizing the model parameters between each node. Exemplary approaches to combining data include parameter averaging and update based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update based data parallelism is similar to parameter averaging except that instead of transferring parameters from the nodes to the parameter server, the updates to the model are transferred. Additionally, update based data parallelism can be performed in a decentralized manner, where the updates are compressed and transferred between nodes.

Combined model and data parallelism 3006 can be implemented, for example, in a distributed system in which each computational node includes multiple GPUs. Each node can have a complete instance of the model with separate GPUs within each node are used to train different portions of the model.

Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques to enable high bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

Exemplary Machine Learning Applications

Machine learning can be applied to solve a variety of technological problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities, such as recognizing faces, to creating new categories of visual abilities. For example, computer vision applications can be configured to recognize sound waves from the vibrations induced in objects visible in a video. Parallel processor accelerated machine learning enables computer vision applications to be trained using significantly larger training dataset than previously feasible and enables inferencing systems to be deployed using low power parallel processors.

Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define the appropriate responses to specific training input. The parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions and enables the deployment of low power inferencing processors in a mobile platform suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks have enabled machine learning approaches to automatic speech recognition (ASR). ASR includes the creation of a function that computes the most probable linguistic sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks have enabled the replacement of the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning procedures can make use of statistical inference algorithms to produce models that are robust to erroneous or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages.

The parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single node training and multi-node, multi-GPU training. Exemplary parallel processors suited for training include the highly-parallel general-purpose graphics processing unit and/or the multi-GPU computing systems described herein. On the contrary, deployed machine learning platforms generally include lower power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

FIG. 30B illustrates an exemplary inferencing system on a chip (SOC) 3100 suitable for performing inferencing using a trained model. The elements of FIG. 30B having the same or similar names as the elements of any other figure herein describe the same elements as in the other figures, can operate or function in a manner similar to that, can comprise the same components, and can be linked to other entities, as those described elsewhere herein, but are not limited to such. The SOC 3100 can integrate processing components including a media processor 3102, a vision processor 3104, a GPGPU 3106 and a multi-core processor 3108. The SOC 3100 can additionally include on-chip memory 3105 that can enable a shared on-chip data pool that is accessible by each of the processing components. The processing components can be optimized for low power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 3100 can be used as a portion of the main control system for an autonomous vehicle. Where the SOC 3100 is configured for use in autonomous vehicles the SOC is designed and configured for compliance with the relevant functional safety standards of the deployment jurisdiction.

During operation, the media processor 3102 and vision processor 3104 can work in concert to accelerate computer vision operations. The media processor 3102 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 3105. The vision processor 3104 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation of processing the frames using a trained image recognition model. For example, the vision processor 3104 can accelerate convolution operations for a CNN that is used to perform image recognition on the high-resolution video data, while back end model computations are performed by the GPGPU 3106.

The multi-core processor 3108 can include control logic to assist with sequencing and synchronization of data transfers and shared memory operations performed by the media processor 3102 and the vision processor 3104. The multi-core processor 3108 can also function as an application processor to execute software applications that can make use of the inferencing compute capability of the GPGPU 3106. For example, at least a portion of the navigation and driving logic can be implemented in software executing on the multi-core processor 3108. Such software can directly issue computational workloads to the GPGPU 3106 or the computational workloads can be issued to the multi-core processor 3108, which can offload at least a portion of those operations to the GPGPU 3106.

The GPGPU 3106 can include processing clusters such as a low power configuration of the processing clusters within the highly-parallel general-purpose graphics processing units described above. The processing clusters within the GPGPU 3106 can support instructions that are specifically optimized to perform inferencing computations on a trained neural network. For example, the GPGPU 3106 can support instructions to perform low precision computations such as 8-bit and 4-bit integer vector operations.

FIG. 31 illustrates another example of a graphics processing unit (GPU) 3105 which includes dedicated sets of graphics processing resources arranged into multi-core groups 3100A-N. The graphics processing unit (GPU) 3105 may be a variant of the graphics processor 300, the GPGPU 1340 and/or any other graphics processor described herein. Therefore, the disclosure of any features for graphics processors also discloses a corresponding combination with the GPU 3105, but is not limited to such. Moreover, the elements of FIG. 31 having the same or similar names as the elements of any other figure herein describe the same elements as in the other figures, can operate or function in a manner similar to that, can comprise the same components, and can be linked to other entities, as those described elsewhere herein, but are not limited to such. While the details of only a single multi-core group 3100A are provided, it will be appreciated that the other multi-core groups 3100B-N may be equipped with the same or similar sets of graphics processing resources.

As illustrated, a multi-core group 3100A may include a set of graphics cores 3130, a set of tensor cores 3140, and a set of ray tracing cores 3150. A scheduler/dispatcher 3110 schedules and dispatches the graphics threads for execution on the various cores 3130, 3140, 3150. A set of register files 3120 store operand values used by the cores 3130, 3140, 3150 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements) and tile registers for storing tensor/matrix values. The tile registers may be implemented as combined sets of vector registers.

One or more Level 1 (L1) caches and texture units 3160 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc, locally within each multi-core group 3100A. A Level 2 (L2) cache 3180 shared by all or a subset of the multi-core groups 3100A-N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 3180 may be shared across a plurality of multi-core groups 3100A-N. One or more memory controllers 3170 couple the GPU 3105 to a memory subsystem 3198 which may include a system memory (e.g., DRAM) and/or a local graphics memory (e.g., GDDR6 memory).

Input/output (IO) circuitry 3195 couples the GPU 3105 to one or more IO devices 3195 such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices 3190 to the GPU 3105 and memory 3198. One or more IO memory management units (IOMMUs) 3170 of the IO circuitry 3195 couple the IO devices 3190 directly to the system memory 3198. The IOMMU 3170 may manage multiple sets of page tables to map virtual addresses to physical addresses in system memory 3198. Additionally, the IO devices 3190, CPU(s) 3199, and GPU(s) 3105 may share the same virtual address space.

The IOMMU 3170 may also support virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 3198). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated in FIG. 31 , each of the cores 3130, 3140, 3150 and/or multi-core groups 3100A-N may include translation lookaside buffers (TLBs) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

The CPUs 3199, GPUs 3105, and JO devices 3190 can be integrated on a single semiconductor chip and/or chip package. The illustrated memory 3198 may be integrated on the same chip or may be coupled to the memory controllers 3170 via an off-chip interface. In one implementation, the memory 3198 comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles of the invention are not limited to this specific implementation.

The tensor cores 3140 may include a plurality of execution units specifically designed to perform matrix operations, which are the fundamental compute operation used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores 3140 may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). A neural network implementation may also extract features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores 3140. The training of neural networks, in particular, requires a significant number matrix dot product operations. In order to process an inner-product formulation of an N× N×N matrix multiply, the tensor cores 3140 may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.

Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores 3140 to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes).

The ray tracing cores 3150 may be used to accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 3150 may include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores 3150 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores 3150 perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores 3140. For example, the tensor cores 3140 may implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores 3150. However, the CPU(s) 3199, graphics cores 3130, and/or ray tracing cores 3150 may also implement all or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising may be employed in which the GPU 3105 is in a computing device coupled to other computing devices over a network or high speed interconnect. The interconnected computing devices may additionally share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

The ray tracing cores 3150 may process all BVH traversal and ray-primitive intersections, saving the graphics cores 3130 from being overloaded with thousands of instructions per ray. Each ray tracing core 3150 may include a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc) to the thread context. The other cores 3130, 3140 may be freed to perform other graphics or compute work while the ray tracing cores 3150 perform the traversal and intersection operations.

Each ray tracing core 3150 may include a traversal unit to perform BVH testing operations and an intersection unit which performs ray-primitive intersection tests. The intersection unit may then generate a “hit”, “no hit”, or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores 3130 and tensor cores 3140) may be freed to perform other forms of graphics work.

A hybrid rasterization/ray tracing approach may also be used in which work is distributed between the graphics cores 3130 and ray tracing cores 3150.

The ray tracing cores 3150 (and/or other cores 3130, 3140) may include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of unique sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores 3150, graphics cores 3130 and tensor cores 3140 is Vulkan 1.1.85. Note, however, that the underlying principles of the invention are not limited to any particular ray tracing ISA.

In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions.

The tensor cores 3140 may support a machine-learning instruction set for executing deep learning instructions/primitives. For example, some embodiments of the tensor cores 3140 execute an instruction that includes various forms of matrix multiplication instructions, dot-product instructions, and multiply-accumulate instructions.

Cache Streaming Apparatus and Method for Deep Learning Operations

Some embodiments of the invention implement data streaming and cache control techniques specifically adapted for deep learning. In particular, these embodiments ensure that data is available when needed at each stage of the deep learning processing pipeline and evicting those cache lines containing data which are no longer needed. In some instances, a cache line may be demoted from a higher cache level (e.g., LSC/L1) to a lower cache level (e.g., L2/L3) when the cache line is not currently needed, but may be at a later time.

Machine learning implementations typically operate on data in multiple passes, such as a forward pass and a back-propagation pass. For example, in online learning, the forward pass needs to store the activations of intermediate layers, ideally without polluting the cache, so that shared data will be available for the backpropagation pass. This can result in writing 32-256 single-precision (32-bit) or 16-bit (half-precision) floating point values per layer (e.g., in Tiny Neural Network settings). Some embodiments of the invention implement hardware-accelerated inferencing per SIMD or SIMT group, where the entire set of operations in the SIMD/SIMT group is usable for issuing these types of writes.

Conversely, in the back-propagation stage, each of these intermediate activations is read exactly once (in reverse order) by one SIMD/SIMT group only, to compute weight derivatives and previous activation derivatives. The data required for back-propagation should therefore be maintained within the cache subsystem, so that it will be available when performing these operations. In contrast, data which is no longer needed should be efficiently released from the cache subsystem to free up storage space.

Referring to FIG. 32 , in one embodiment, data streaming hardware logic 3230 is closely-coupled to the compute units 3210 of the machine-learning processor to ensure that the data needed at each machine-learning stage is streamed in and out of the cache subsystem 3235 as it is needed. In the illustrated example, the cache subsystem 3235 includes an L0 cache 3200, an L1/LSC 3201, and an L2 cache 3202, although the underlying principles of the invention are not limited to any particular cache hierarchy.

In some embodiments, the compute units (CUs) 3210 include SIMD/SIMT execution architectures which execute an instruction on different data across multiple lanes (e.g., 32 lanes, 64 lanes, 128 lanes, etc). ML data management logic 3210, which may be implemented in hardware, software executed on the CUs, or any combination thereof, sends commands and/or notifications to the data streaming hardware 3230, which responsively performs cache fill and cache flush operations to specified levels of the cache subsystem 3235—to ensure that the ML data 3204 is available within the cache subsystem 3235 by the time it is needed.

In the specific example in FIG. 32 , ML data 3204 is prefetched to the L2 cache 3202 in response to one or more commands 3215 issued by the ML data management logic 3210. By way of example, and not limitation, the command 3215 may include a prefetch command which identifies a specified set of data 3204 and a specific cache level (e.g., a prefetch to the L2 cache 3202 is shown as an example).

Referring to FIG. 33 , in some embodiments, the ML data management logic 3210 programs the data streaming hardware 3230 at the start of a ML sequence via a set of configuration registers 3310. For example, the command 3215 issued by the ML data management logic 3210 may store threshold or watermark values within the configuration registers 3310 to indicate an amount of cache storage which can be consumed by different stages of the machine-learning sequence (e.g., forward-propagation, back-propagation, etc). When the watermark value is reached, the data streaming hardware logic 3230 may determine that the next stage of the ML sequence has been reached and evict data which has not otherwise been marked as shared.

Once programmed, the data streaming hardware 3230 monitors data usage by the ML sequence and streams the various forms of ML data in and out of the cache subsystem 3235 in accordance with the programming—thereby ensuring that the ML data will be available to the CUs at the time it is needed.

Returning to the above online learning example, the data streaming hardware 3230 prefetches the ML data required for the forward-propagation sequence and ensures that any shared data is maintained within the cache subsystem 3235 until it is used by the back-propagation sequence. For example, the data streaming hardware 3230 may tag the cache lines in which shared data required by the back-propagation sequence is stored, or otherwise perform operations to ensure that the cache lines will not be polluted or evicted prior to the back-propagation pass. One or more bits may be set in the configuration registers 3310 to indicate that tagging is being used. In these implementations, the tags indicate that the shared data is to be stored until it is read during the back-propagation pass. Once the shared ML data is consumed by the back-propagation pass, including at least some of the activation data, the data streaming hardware 3230 may flush the data from the cache subsystem 3235 (e.g., by changing the tags to “invalid” to effectively remove the cache lines), thereby ensuring that the storage space in the cache subsystem 3235 is released for subsequent ML operations.

As mentioned, forward-propagation may result in writing 32-256 single-precision (32-bit) or 16-bit (half-precision) floating point values per layer to the cache subsystem 3235. The commands 3215 issued by the ML data management logic 3210 may specify a particular cache level in which the activation data is to be stored (e.g., the L2 cache 3202, L1/LSC 3201, L0 cache, etc).

Using these techniques, the data streaming hardware 3230 (potentially programmed via commands from ML data management logic 3210) hides the latency associated with data access operations by prefetching the ML data 3204 into the cache subsystem 3235 so that it is available when needed and also by ensuring results produced by a first sequence of ML operations (e.g., forward-propagation) do not pollute the cache subsystem 3235 by overwriting shared data needed by the second sequence of ML operations (e.g., back-propagation). In the event that results produced by the first ML operations are written back to memory 3205 (e.g., because space in the cache subsystem 3235 is needed for interim operations), the data streaming hardware 3230 may prefetch the results back into the cache subsystem 3235 so they will be available at the time they are needed.

A shared local memory (SLM) 3250 may also be used in the embodiments described herein. In these embodiments, the SLM is an on-chip high speed memory which stores data that can be shared across threads in a thread group. In these implementations, since the activation data used for back-propagation from multiple instances may over-subscribe the SLM 3250, the cache subsystem 3235 may be used instead of the SLM 3250. For example, the cache subsystem 3235 may be used with global atomics to consolidate data from multiple instances for performing weight updates per thread group or batch.

In some embodiments, a least recently used (LRU) or other cache management policy can cause earlier activations during forward-propagation to a lower cache level (e.g., from the L0 cache 3200 to the L1/LSC 3201 or L2 cache 3202). During back-propagation, the data may be read from the lower cache level (or any cache level) using an invalidate on read (IOR) transaction which invalidates the data in the cache subsystem 3235 once it is read. Using these techniques, the L1 cacheability of data can be controlled on per-message basis. For example, if the compiler knows that a given activation is not going to be needed right away, it may skip caching in the L1/LSC 3201 in favor of streaming into the L2 cache 3202 and then brought back with a prefetch operation/command. For the last few (or just one) layer during back-propagation, that data may be stored into the L1/LSC 3201. In any case, invalidate-on-read transactions work to free up lines proactively instead of letting them be victimized by the LRU (or other) cache management policy.

In some instances it may not be clear whether the activation data and other data generated during forward-propagation will be used right away. In such cases, the data streaming hardware logic 3230 may adjust the caching policy for the LSC/L1 3201 (or use the existing policy) to implement writethrough mode, thereby causing the forward-propagation data to be simultaneously updated to the L1/LSC cache 3201 and memory 3205. In some embodiments, write-combining techniques are also used (e.g., in combination with writethrough). In these implementations, the forward-propagation data is combined and temporarily stored in a write combine buffer (WCB) and written to memory in a burst mode instead of writing each individual piece of data immediately.

As mentioned, the data streaming hardware logic 3230 flushes data which is no longer needed from any level of the cache subsystem 3235, to ensure that storage space is available for subsequent operations. The flush operations may be performed at various levels of granularity, and/or in various operational modes, depending on the current stage of the machine-learning process.

For example, in certain modes of operation, the L1/LSC 3201 (or other level of the cache subsystem 3235) flushes all dirty cache lines indiscriminately. In other modes, flushes are performed with more granularity. For example, in some embodiments, the data streaming hardware logic 3230 selects a “workgroup” mode to flush only those cache lines which become dirty as a result of writes coming from the current machine-learning workgroup. In another mode, the data streaming hardware logic 3230 annotates writes to the cache subsystem 3235 with a tag (e.g., using one or more cache line bits). The flush operations specified by the data streaming hardware logic 3230 may then flush only those cache lines marked with a given tag.

In another mode of operation, the data streaming hardware logic 3230 may specify flushes for cache lines in any level of the cache subsystem 3235 with a specified cach xeline-aligned address range (e.g., identified by an address space identifier such as a PASID value). This mode is particularly useful for situations where a workgroup's output range is contiguous.

As mentioned, the cache writing and cache flushing techniques described above may be implemented at any cache level within the cache subsystem 3235 including the L0 cache 3200, the L1/LSC 3201, and/or the L2 cache 3202.

Apparatus and Method for Scheduling Inferencing Tasks

As illustrated in FIG. 34 , in some embodiments, one or more compute units 3210 execute inferencing operations on SIMD/SIMT execution circuitry 3401. As described herein, the SIMD/SIMT execution circuitry 3401 comprises vector registers, ALUs, and other parallel execution circuitry to simultaneously execute instructions across multiple threads/tasks as scheduled and dispatched by dispatcher circuitry 3420.

The execution hardware 3401 may execute inferencing program code 3410, for example, per pixel, per ray hit, etc. In some cases, inference execution may require full SIMD groups to be spawned for a single task or thread, to allow collaborative hardware-accelerated matrix multiply, streaming, etc. Some tiny-NN implementations may also use shared memory 3250 for programming with abstractions using pointer addressing (modular code for layers, activations, etc) while avoiding the cost of global memory reads/writes.

Neural inferences are used for hit shading in some embodiments, using the same underlying execution architecture for different neural network weights based on different object characteristics (e.g., such as the object material). This is analogous to classic graphics execution where the same shader may be used with different textures. The compute units 3210 extract coherence based on bound resources and, with random access programming capabilities, some embodiments perform tagging of similar tasks for coherence extraction (e.g. when inputs/weights are all read from the same texture or even volume texture).

Some embodiments of the compute units 3210 support changing SIMD/SIMT execution modes for mixing neural inference execution with graphics shading techniques. These embodiments can also leverage current task graph systems, for example, by subdividing threads/tasks between neural and non-neural boundaries.

In some embodiment, a combination of compiler techniques and extensions to the on-chip sorting capabilities of BTD can be used to extract/retain both code execution coherency and data coherency. In these embodiments, the dispatcher 3420 is a BTD-aware dispatcher as described herein and in various co-pending related applications, which efficiently manages the execution of divergent threads within SIMD/SIMT thread groups.

The SIMD/SIMT execution circuitry 3401 operates in accordance with an execution model of N work-items (which may be rays, pixels, etc) processed in parallel (e.g., where N=32, 64, 128, etc). Each active item is allocated a stackID/handle that identifies the work-item and a corresponding slot in the working set memory—referred to as a stack.

In some embodiments, shader/inference routines can be decomposed into phases to be executed in either SIMT or SIMD mode on the SIMD/SIMT execution circuitry 3401. Parts of the code to be executed in a particular mode can be explicitly marked by the programmer or automatically compiler-detected. Such phases can be specified in a descriptor that includes a pointer to the code to be executed and resources that are accessible during code execution, such as textures, constant buffers, UAVs, RSVs, etc. In some embodiments, the descriptor 3411 also specifies execution mode and width. For example, SIMD or SIMT operation may be specified, together with the requested SIMD/SIMT width. In one embodiment, the descriptor 3411 is uniquely-identified and referred to as a 64-bit wide BTD sorting key.

In some embodiments, at the execution mode/phase boundaries, code may be injected (e.g., by a compiler) to store all live ranges/variables of the current work-item to its corresponding stack. Subsequently, a message 3450 is generated with a payload defining what code to execute next. For example, if the current execution mode is SIMD, the message 3450 includes a tuple of (stackID, BTD sorting key); if the current execution mode is SIMT, a tuple (stackID, BTD sorting key) is provided for each active execution lane in the execution circuitry 3401.

In one embodiment, the message is received and processed by the BTD-enabled dispatcher 3420 when the current shader phase terminates. Upon receipt of the BTD message, the BTD-enabled dispatcher 3420 extracts valid (stackID, BTD sorting key) tuples, sorts them on-chip by their BTD sorting keys, and accepts their stackIDs into corresponding sets. The BTD-enabled dispatcher 3420 reads from memory descriptors 3411 corresponding to each active BTD sorting key and keeps accepting new stackIDs/handles up to the limit given in the corresponding descriptor.

The BTD-enabled dispatcher 3420 begins spawning threads for execution on the SIMD/SIMT execution circuitry 3401 in response to one or more triggering events. This can include, for example, when a limit of stackID/handles per-BTD sorting key has been reached, a timer is triggered, or a flush operation was requested.

Referring to FIG. 35 , depending on which execution mode was specified in the corresponding descriptor (SIMT or SIMD), a single thread 3501 is scheduled/dispatched for execution (SIMT) or a separate EU thread 3520 is spawned for each of the collected stackIDs/handles (SIMD) 3506 (numbered 1-4 in the example). In some instances, the BTD-enabled dispatcher 3420 and other shared functions ensure that the threads are allocated to all available EU threads with the highest priority (i.e., to ensure no interruptions for execution of other EU threads).

This implementation assures that even though each of the K threads are scheduled for execution on a separate EU thread 3520, all of them execute the same code at possibly the same rate. Such an execution maximizes data and cache coherency extraction. The above sequence of operations may be repeated for all subsequent phases of the inference/shading routine.

The sorting logic 3505A-B (e.g., BTD on-chip sorting logic) may distribute work within a single compute unit or core. The sorting logic 3505A-B may include a global sorting capability that constantly monitors BTD sorting keys being active on each of compute units/cores. The sorting logic 3505A-B examines BTD sorting keys corresponding to incoming tasks and distributes them to individual CUs/cores based on presence of the BTD sorting keys in each CU/Core. This approach helps maximize both sorting effectiveness and data access coherency.

In some embodiments, a scheduler 3490 also monitors utilization of L1 cache/LSC 3201 (and/or other cache levels) and takes its utilization into account when distributing work across CUs/cores. As previously described, mainlining a working set that fits into L1 caches is critical to achieving high overall performance of the inference implementation.

EXAMPLES

The following are example implementations of different embodiments of the invention.

Example 1. An apparatus comprising: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

Example 2. The apparatus of example 1 wherein the dispatching hardware logic is to determine whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode by reading a descriptor associated with the current phase.

Example 3. The apparatus of example 2 wherein the descriptor is to be automatically generated by a compiler or specified by a user.

Example 4. The apparatus of claim 3 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.

Example 5. The apparatus of example 4 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.

Example 6. The apparatus of example 2 wherein the dispatching hardware logic is to receive a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.

Example 7. The apparatus of example 6 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items.

Example 8. A method comprising: executing inferencing routines on a plurality of compute units (CUs), an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; determining, by dispatching hardware logic, whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode; and dispatching instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

Example 9. The method of example 8 wherein determining whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode is performed by reading a descriptor associated with the current phase.

Example 10. The method of example 9 wherein the descriptor is to be automatically generated by a compiler or specified by a user.

Example 11. The method of claim 10 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.

Example 12. The method of example 11 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.

Example 13. The method of example 9 further comprising: receiving, by the dispatching hardware logic, a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.

Example 14. The method of example 13 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items.

Example 15. A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: executing inferencing routines on a plurality of compute units (CUs), an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; determining, by dispatching hardware logic, whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode; and dispatching instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

Example 16. The machine-readable medium of example 15 wherein determining whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode is performed by reading a descriptor associated with the current phase.

Example 17. The machine-readable medium of example 16 wherein the descriptor is to be automatically generated by a compiler or specified by a user.

Example 18. The machine-readable medium of example 17 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.

Example 19. The machine-readable medium of claim 18 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.

Example 20. The machine-readable medium of example 16 further comprising program code to cause the operations of:

receiving, by the dispatching hardware logic, a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.

Example 14. The machine-readable medium of example 13 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items.

Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.).

In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow. 

What is claimed is:
 1. An apparatus comprising: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.
 2. The apparatus of claim 1 wherein the dispatching hardware logic is to determine whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode by reading a descriptor associated with the current phase.
 3. The apparatus of claim 2 wherein the descriptor is to be automatically generated by a compiler or specified by a user.
 4. The apparatus of claim 3 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.
 5. The apparatus of claim 4 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.
 6. The apparatus of claim 2 wherein the dispatching hardware logic is to receive a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.
 7. The apparatus of claim 6 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items.
 8. A method comprising: executing inferencing routines on a plurality of compute units (CUs), an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; determining, by dispatching hardware logic, whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode; and dispatching instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.
 9. The method of claim 8 wherein determining whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode is performed by reading a descriptor associated with the current phase.
 10. The method of claim 9 wherein the descriptor is to be automatically generated by a compiler or specified by a user.
 11. The method of claim 10 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.
 12. The method of claim 11 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.
 13. The method of claim 9 further comprising: receiving, by the dispatching hardware logic, a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.
 14. The method of claim 13 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items.
 15. A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: executing inferencing routines on a plurality of compute units (CUs), an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; determining, by dispatching hardware logic, whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode; and dispatching instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.
 16. The machine-readable medium of claim 15 wherein determining whether the current phase of the inferencing routine is to be executed in SIMD or SIMT mode is performed by reading a descriptor associated with the current phase.
 17. The machine-readable medium of claim 16 wherein the descriptor is to be automatically generated by a compiler or specified by a user.
 18. The machine-readable medium of claim 17 wherein the execution circuitry comprises a plurality of arithmetic logic units (ALUs) configurable to concurrently process a corresponding plurality of work-items in accordance with the SIMD mode or the SIMT mode.
 19. The machine-readable medium of claim 18 wherein each work-item is allocated a unique identifier (ID) to identify the work-item and a corresponding stack.
 20. The machine-readable medium of claim 16 further comprising program code to cause the operations of: receiving, by the dispatching hardware logic, a message from scheduling logic to determine whether a current phase of an inferencing routine, the message including a pointer to the descriptor.
 21. The machine-readable medium of claim 13 wherein the message includes a unique identifier (ID) to identify a work-item of the inferencing routine and a corresponding sorting ID to be used to sort the work-item relative to one or more other work-items. 